This paper presents a small-sized, low-power gas sensor system combining a high-electron-mobility transistor (HEMT) device and readout integrated circuit (ROIC). Using a semiconductor-based HEMT as a gas-sensing device, it is possible to secure high sensitivity, reduced complexity, low power, and small size of the ROIC sensor system. Unlike existing gas sensors comprising only HEMT elements, the proposed sensor system has both an ROIC and a digital controller and can control sensor operation through a simple calibration process with digital signal processing while maintaining constant performance despite variations. The ROIC mainly consists of a transimpedance amplifier (TIA), a negative-voltage generator, and an analog-to-digital converter (ADC) and is designed to match a minimum target detection unit of 1 ppm for hydrogen. The prototype ROIC for the HEMT presented herein was implemented in a 0.18 µm complementary metal–oxide–semiconductor (CMOS) process. The total measured power consumption and detection unit of the proposed ROIC for hydrogen gas were 3.1 mW and 2.6 ppm, respectively.

A time-interleaved noise-shaping (TINS) successive approximation register (SAR) analog-to-digital converter (ADC) for wide bandwidth, high resolution, and low power consumption is proposed. A fully passive switched-capacitor integrator based on a single capacitor and a single-input comparator is adopted in the proposed three-channel structure for 1st-order noise shaping with low power consumption. The SAR conversion is split into coarse and fine conversions to allow noise shaping in the time-interleaved structure to maximize the bandwidth. In addition, a dynamic weight averaging method for three channels is introduced to suppress the effect of capacitor mismatch. The prototype ADC is implemented in a 28-nm CMOS process and achieves a signal-tonoise and distortion ratio of 65.37 dB, a bandwidth of 75 MHz at a sampling rate of 600 MHz, and a power consumption of 4.015 mW with a 1.1 V supply. A Walden figure-of-merit (FoM) of 17.65 fJ/conv.-step and a Schreier FoM of 168.1 dB show that the proposed TINS SAR ADC improves speed and accuracy with good power efficiency.

This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter. This consequently achieves the high-power efficiency of the ADC. The simulated SNDR is 79.97 dB; it achieves a 12.5-MHz BW at a 175-MHz sampling rate, with OSR of 7. The total power consumption of the ADC is 4.27 mW at a 1.1-V supply. The ${\mathrm{FoM}}_{\mathrm{S},\mathrm{SNDR}}$ is 174.6 dB. The proposed structure achieves high resolution and wide bandwidth with good energy efficiency.