A 0.8-V resistor-based CMOS temperature sensor in 65-nm CMOS process with low supply sensitivity is presented. The temperature-to-voltage conversion gain is maximized by utilizing two types of on-chip resistors with positive and negative temperature coefficient. Reusing the resistor sensor frontend as a reference, the voltage generator of the subsequent A/D converter inherently removes the supply dependence of temperature-to-digital conversion. A 10-bit sub-ranging A/D converter employing 5-bit amplifying interpolation D/A converter enables low-voltage and low-noise A/D conversion. Over a range of -45 °C ~ 85 °C, the proposed sensor achieves 0.12 °C _rms temperature resolution with a conversion time of 10 μs. After a 2-point calibration, the sensor achieves an inaccuracy of less than +1.6/-1 °C while consuming 47 μW from 0.8-V supply voltage. Measured supply sensitivity is 0.28 °C/V over 0.6 ~1.2 V, which is one of the lowest ever reported among sub-1-V temperature-to-digital converter designs.

A pipelined noise-shaping successive approximation register (NS-SAR) ADC with 1–2 multistage noise-shaping (MASH) structure is presented. Two-stage pipelined structure consisting of 5 bit NS-SAR and 4 bit NS-SAR quantizers enables 3rd-order noise-shaping. A single operational transconductance amplifier (OTA) is shared by an integrator for noise-shaping and a residue amplifier for pipelining to maximize the power efficiency. The measured dynamic range (DR) is 84.6 dB when the sampling rate is 83.3 MS/s, bandwidth is 4 MHz, and power consumption is 3.5 mW showing Schreier figure-of-merit (FoM _S,DR ) of 175.2 dB. The proposed ADC structure greatly relaxes design requirement of each SAR quantizer and can achieve high resolution and wide bandwidth with good power efficiency.

This paper proposes a 750-Mb/s to 3.0-Gb/s dual-mode (full and half rate) referenceless clock and data recovery (CDR) circuit in a 65-nm CMOS process. The dual-mode deadzone-compensated frequency detector (DC-FD) and the digital calibration of both bank and control voltage of voltage-controlled oscillators (VCOs) allow precise frequency acquisition even with high input jitter. The dual-mode scheme extends supported data rates, and the temperature compensation technique allows uninterrupted video transmission with a bit error rate (BER) below 10 ^-12 over a wide temperature range from -20 °C to 120 °C.

This paper presents a 4th order 20kHz 16MHz programmable-bandwidth active RC filter. For high linearity performance, the gain-boosted opamp in the biquad adopts negative resistance in auxiliary amplifiers to achieve high-gain without requiring extra common-mode feedback amplflifier, thereby minimizing total current and design complexity. To further enhance the filter linearity, a source follower using native NMOS transistors generates common-mode output without adding extra resistive loading to the opamp output. The prototype filter is fabricated in 65nm CMOS and occupies 0.098mm2. It features three programmable cutoff frequencies of 20kHz, 2MHz, and 16MHz and achieves IIP3 of 22.1dBm while consuming 19mW under 1.8V supply. The measured figure-of-merit considering the linearity, power, bandwidth, noise, and silicon area shows that the presented filter achives best-in-line compromise among conflicting design metrics.

This paper presents comprehensive analyses of power-performance tradeoffs in current-mode logic (CML)-based transmitters via equation-based optimization and provides practical design guidelines that can help achieving optimum power efficiency. An accurate equation-based optimization framework was developed for this purpose, and using this framework, key circuit-level design parameters were found with specific design specifications and process technologies. The proposed optimization framework can determine optimum clock edge-rate (i.e., ratio of rise/fall time to clock period) and inter-stage voltage swings that enable significant power savings without affecting performance. Various transmitter design tradeoffs were analyzed for 45-nm, 65-nm, and 90-nm technologies considering data rate, clock edge-rate, and inter-stage swing optimization. Based on the analysis results, we determined the most energy-efficient data rate that can be achieved with acceptable power overhead for each technology node. Also, we identified the optimal clock edge-rate and inter-stage voltage swings in CML gates that achieved minimum transmitter power dissipation. Our analysis results indicate that, when properly optimized, overall transmitter power consumption can be reduced by up to 43% with inter-stage swing optimization with all other design constraints held constant.

This article presents a 6-bit 1.1 GS/s asynchronous charge-injection SAR (ci-SAR) analog-to-digital-converter (ADC) achieving an unprecedented area efficiency of 0.0048 GS/s/ $\mu$ m $^{2}$ per slice. A current-reduced charge injection cell (CIC) enables a small input capacitance of 8.5 fF, which helps extend the effective resolution bandwidth (ERBW) to 7 GHz. A replica-based feedback loop desensitizes the full-scale variations on process, voltage, and temperature (PVT) conditions. A common-mode shifting scheme relaxes the dynamic offset issue of the comparator inherent in monotonic switching. The chip is fabricated in a 28 nm CMOS process with an active area of 227 $\mu$ m $^{2}$ . The peak SNDR is 35.2 dB with FOM $_{\text{w}}$ $=$ 25.5 fJ/conv.-step. The measured SNDR drops by less than 2.32 dB over $-$ 40 $^{\circ}$ C to 100 $^{\circ}$ C temperature variation and 0.9 to 1.1 V supply variation.