This paper presents a 28-GHz low phase noise voltage-controlled oscillator (VCO) in a 65-nm CMOS process for 5G communication applications. With the capacitive splitting and transformer feedback techniques, theoretical analysis and simulations are undertaken for the proposed oscillator, proving that its negative Gm can be enhanced over the interested frequency range and reduced at the harmonic frequencies. Moreover, the proposed oscillator startup performance is analyzed, and its tank quality factor, transient and phase noise performance are simulated. With 4-bit switch capacitors and varactors, the proposed VCO achieves a tuning range from 25.7 to 29.7 GHz, consuming 10.8 mW from a 0.9-V supply voltage. With a wideband common-source buffer, the output signal power is around 1 dBm. At 26.5 GHz, the proposed VCO achieves low phase noise of -105.8 dBc/Hz at 1-MHz offset and -130 dBc/Hz at the 10-MHz offset, respectively.

By combining the transformer feedback and VCO multi-core techniques, this paper presents a 0.5 V low voltage 28.6-to-36.2 GHz dual-core VCO for 5G applications. Based on the transformer feedback topology, with the power-ground interconnect inductor and embedded decouple capacitor, the second harmonic real impedance is achieved at the VCO cross-couple pair source terminal. Accordingly, the common-mode current path is reduced and the signal symmetry improved, suppressing the flicker noise up conversion. With a 4 bit switch capacitors and varactors, the proposed VCO achieves a 28.6-to-36.2 GHz (23.5 %) tuning range, and its flicker noise corner is from 250 to 980 kHz. Fabricated in a 65nm CMOS process, the VCO consumes 4.6mW from a 0.5 V supply voltage with a core area of about 0.24× 0.5 mm2. At 31 GHz, the proposed VCO achieves a phase noise of -103 dBc/Hz@1MHz offset, resulting in a figure-of-merit (FoM) of -186.2 dBc/Hz and tuning range figure-of-merit (FoMT) of -193.6 dBc/Hz, respectively.

This article presents a 32-GHz frequency-modulated continuous wave (FMCW) modulator based on the phase-locked loop (PLL) with nested sub-PLL structure in a 65-nm CMOS process. With the sub-PLL, the low-pass effect in phase domain is realized, reducing the noise folding effect, quantization noise, and spurs due to the delta sigma modulator (DSM). To achieve good stability and phase noise performance, both the phase-domain model and the phase noise model are analyzed and simulated. Based on these models, the chirp linearity is discussed and simulated, which helps to determine the design parameters and verifies the linearity improvement. The measurement results illustrate that in fractional-N mode, the nested-PLL achieves the phase noise of -91 dBc/Hz at 1-MHz offset frequency and the fractional spurs of less than -54 dBc at 30.78-GHz output frequency. In FMCW mode, the proposed modulator achieves a triangular chirp with 1.08-2.16-GHz bandwidth at about 32-GHz center frequency. In addition, the measured root mean square (rms) frequency errors of 400 and 770 kHz are achieved with the ramp slopes of 1.08 GHz/93 μs and 2.16 GHz/93 μs, respectively. Measurement results prove the improvements of the phase noise and chirp linearity with the sub-PLL. Including all pads, the chip occupies a silicon area of 1.5 mm², and consumes 62-mW dc power.

A fractional-N divider with delta-sigma modulator and phase-lag selector for phase-locked loop (PLL) is presented in this paper. Basically, the fractional-N frequency divider consists of a pre-divide-by-2 frequency divider (Div. 2), a phase selector (PS) with the auxiliary circuit, a multi-modulus frequency divider (MMD) and a delta-sigma modulator (DSM). With a 65nm CMOS process, the high speed circuit, like Div. 2, and low power circuits, like MMD and DSM, are designed. The proposed divider achieves 8.5GHz maximum operating frequency with 32-256 division range and less than 25 Hz frequency resolution. The divider power consumption is less than 8mA from a 1.2 V power supply at 6GHz.

An 11-GHz ultra-fast wideband frequency-modulated continuous-wave (FMCW) chirp generator with high linearity is presented for rapid walk-through imaging. To facilitate fast frequency modulation while reducing phase noise, a digital-to-time converter (DTC)-based sub-sampling phase-locked loop (SSPLL) with two-point modulation (TPM) technique is leveraged. Integrated with a ramp integrator, the proposed second-order curve-fitting (2nd-CF) digital predistortion (DPD) technique could remarkably mitigate the nonlinearities in the frequency modulation path while significantly reducing the hardware complexity. Meanwhile, a ramp tracker is parallelly utilized to initialize the lookup table (LUT) of DPD for a robust chirp linearity calibration. To reduce the idle time of the ultra-fast chirp without affecting its linearity, a modified DTC modulator is designed to achieve zero phase error at large frequency hopping moments. Furthermore, to achieve robust background calibrations in SSPLL, a voltage tracking loop (VTL) with a hold function is proposed to extract the phase-error sign and cooperate with the LUT to ensure an orderly convergence of the DPD. Fabricated in a 65-nm CMOS process, the FMCW chirp generator occupies a core area of 1.2 mm² and consumes 50.8 mW. The measured maximum chirp bandwidth is 2.4 GHz, corresponding to 21.4% of the center frequency. A maximum chirp slope of 2.3 GHz/ $\mu $ s is achieved with 2.3-GHz chirp bandwidth, 1- $\mu $ s chirp duration, and 50-ns idle time, and the largest measured rms frequency error is 1198 kHz for sawtooth and triangular chirps, corresponding to 0.052% of the chirp bandwidth.

To improve the PLL in-band phase noise and setting time, improved nonlinear phase frequency detector (PFD), charge-pump (CP) and level shifter (LSF) circuits are proposed in this paper, achieving larger than 19V/ns switching slew rate from 0.15 to 1.65V of LSF and less than 2.2 pA/√Hz noise density at 1MHz offset of CP, respectively. With a 65nm CMOS process, a 12-18GHz phased-locked loop is designed, achieving in-band phase noise of -103.5dBc/Hz @100KHz, settling time of lower than 4us, respectively.