This article presents an optimized design of a low-noise transimpedance amplifier (TIA) with high linearity for use in the downlink receiver of a remote antenna unit (RAU). The aim of this design is to be used in a cost-effective indoor distributed antenna system (DAS) for WLAN transmission using a mixed fiber-wireless system. The circuit topology consists of a fully differential shunt–shunt feedback TIA with digitally programmable transimpedance. An open-loop gain compensation technique is used to maintain stability and constant bandwidth (BW). The TIA has been fabricated in 65 nm CMOS technology with a 1.2 V voltage supply. The total power consumption of the TIA is 6 mW. A complete electrical and optical characterization with a 1550 nm PIN photodiode has been performed to demonstrate the reliable 54 Mb/s 802.11a WLAN transmission achieved with an error vector magnitude (EVM) lower than 3% for a 20 dB optical input range.

In this work, we have used a new concept of sensor-based seed generator in order to generate the keys for a stream cipher based on a new algorithm mixing a Skew Tent Map and a Linear Feedback Shift Register. The cryptosystem has been implemented in a Xilinx Virtex 7 FPGA and has been proven to be fast and secure for application in IoT networks.

This paper presents an optimization methodology for inductorless noise-cancelling CMOS Low-Noise Amplifiers (LNA), whose performance typically depends on a tight balance in the design of two transistor stages. Due to the different functions of the two parts, noise-cancelling amplifiers become very difficult to analyze in detail by closed-form expressions or straight simulations: each section significantly affects the results of the other. In addition, opposed specifications, such as gain and cut-off frequency, suppose another grade of complexity due to the interplay of the two branches of the circuit. As a solution, the proposed methodology uses a visualization of the design window in 2-dimensional space to optimize the different parameters of the specifications without compromising the others. All specification constraints are represented in a single figure instead of one graph per parameter. Compared with most optimization methods, the design window methodology observes the design span instead of isolated design points that might not guarantee feasibility. Furthermore, as a simulation-driven exploration method, it benefits from complete device models with high-order effects that would be too complex to include in analytical expressions but critical to achieving maximum efficiency. As an example of the method, the paper describes the optimization of the well-known CS-CG noise-cancelling LNA in 65-nm standard CMOS technology. Final post-layout simulations report very competitive results with a 3.7-dB noise figure, a 17-dB gain, and a cut-off frequency above 7 GHz.

A highly-linear low-noise transimpedance amplifier (TIA) with programmable gain for intermediate frequency-over-fiber (IFoF) communications is presented in this paper. It has been fabricated in a 65-nm RF CMOS technology for use in the downlink receiver of remote antenna units for a cost-effective distributed antenna system. The topology consists of a shunt-shunt feedback TIA with open-loop gain control to ensure constant bandwidth, while the transimpedance can be linear-in-dB programmed from 60 to 76 dBO. The IFoF transmission is achieved with a very low error vector magnitude below 2% over an input dynamic range from -16 dBm up to +4 dBm optical power. The TIA shows an equivalent input noise of 8 pA/√Hz at 500 MHz with a bandwidth of 700 MHz. The TIA presents a power consumption of 6 mW from a single supply voltage of 1.2 V, while the total power consumption including the output driver is 19 mW.

This work proposes a new approach to design a simple and effective LNA reaching very competitive results in 1.2V 65-nm standard CMOS technology. The proposed design uses a transconductance enhancement technique to achieve 2.3 dB of noise figure at the 5 GHz band. The paper exposes the advantages of a reduced number of devices in the circuit and analyses the topology. Simulations with complete technology models and statistical analysis are presented for more precise results.