A novel silicon on insulator (SOI)-lateral trench insulated gate bipolar transistor (LTIGBT) featuring a self-biased pMOS (SBP), named SBP-LTIGBT, is proposed and investigated. The gate and drain of SBP are shortly connected with emitter electrode, and the source is connected with the P-buried, which introduces automatically turn-off and turn-on function. At the forward conduction state, the SBP is turned off when ${V}_{\text {GS,P}} > {V}_{\text {TH,P}}$ , and the SBP-LTIGBT shows the same electrical characteristics as conventional LTIGBT. The SBP is automatically turn-on with reduced saturation current when ${V}_{\text {GS,P}}< {V}_{\text {TH,P}}$ . At the switching state, the SBP is always turned on to accelerate the extraction of the excessive carriers; consequently, the turn-off loss ${E}_{\text {OFF}}$ is reduced. As a result, the tradeoff relationship between forward conduction voltage ${V}_{\text {ON}}$ and ${E}_{\text {OFF}}$ is largely improved. The short-circuit tolerance time ( ${T}_{\text {SC}}{)}$ of the SBP-LTIGBT is $10.5~\mu \text{s}$ , which is extended by 3.4, 2, and 1.4 times longer than that of LTIGBT with triple-RESURF (TR-LTIGBT), LTIGBT with double-RESURF (DR-LTIGBT), and conventional LTIGBT (C-LTIGBT), respectively. Furthermore, when ${V}_{\text {ON}}$ is 1.4 V, ${E}_{\text {OFF}}$ of the SBP-LTIGBT is 0.36 mJ/cm2, which is reduced by 73%, 60%, and 51% than that of C-LTIGBT, DR-LTIGBT, and TR-LTIGBT, respectively.

An Extended Superjunction (SJ) Gate (ESG) Lateral Double-diffused Metal–Oxide Semiconductor (LDMOS) with full bulk electron accumulation in the drift is proposed, and the physical mechanism is investigated by the SENTAURUS. It features a Fin Gate including Planar Gate (PG) and ESG: the ESG is formed by the P-Pillar and two integrated back-to-back diodes $\text{D}_{{2}}$ and $\text{D}_{{1}}$ , then the gate potential ${V}_{\text {GS}}$ is extended through the whole P-Pillar. Additionally, the gate oxide ${W}_{\text {oxide}}$ is inserted between the P- and N-Pillars of the SJ. At the ON-state, the 3-D electron channels are produced at the P-well by the Fin Gate, and the extra bulk accumulation effect is induced at the sidewalls of the N-Pillar by the positive ${V}_{\text {GS}}$ of the ESG, which can significantly decrease the ${R}_{\mathrm{\scriptstyle {ON, SP}}}$ . At the OFF-state, the N- and P-Pillars deplete from each other through the gate oxide ${W}_{\text {oxide}}$ like the conventional SJ. The 3-D simulation results show that the BV and ${R}_{\mathrm{\scriptstyle {ON, SP}}}$ are 171 V and 0.49 $\text{m}\Omega \cdot \text {cm}^{{2}}$ , respectively. The FOM is high up to 59.6 MW/cm ² , which breaks through the silicon limit of the RESURF.

Realizing the anisotropic deep trenching of GaN without surface damage is essential for the fabrication of GaN-based devices. However, traditional dry etching technologies introduce irreversible damage to GaN and degrade the performance of the device. In this paper, we demonstrate a damage-free, rapid metal-assisted chemical etching (MacEtch) method and perform an anisotropic, deep trenching of a GaN array. Regular GaN microarrays are fabricated based on the proposed method, in which CuSO₄ and HF are adopted as etchants while ultraviolet light and Ni/Ag mask are applied to catalyze the etching process of GaN, reaching an etching rate of 100 nm/min. We comprehensively explore the etching mechanism by adopting three different patterns, comparing a Ni/Ag mask with a SiN mask, and adjusting the etchant proportion. Under the catalytic role of Ni/Ag, the GaN etching rate nearby the metal mask is much faster than that of other parts, which contributes to the formation of deep trenches. Furthermore, an optimized etchant is studied to restrain the disorder accumulation of excessive Cu particles and guarantee a continuous etching result. Notably, our work presents a novel low-cost MacEtch method to achieve GaN deep etching at room temperature, which may promote the evolution of GaN-based device fabrication.

A Reverse-Conducting LIGBT integrated with dual Self-Driving MOSFET (SDM), named SDM-LIGBT is proposed and investigated by the SENTAURUS. The SDM1 and SDM2 are located at the Emitter and Collector side, respectively. The Gate and the Drain of the SDM1 are shortly connected together to the Emitter of the LIGBT, and the Gate and the Drain of the SDM2 are shortly connected with the N-buffer. Consequently, the dual SDM is driven by the $\textit{V}_{\text{EC}}$ without an extra gate signal. At the forward conduction, the dual SDM is turned off, and the SDM-LIGBT works like conventional LIGBT without a snapback effect. Moreover, the $\textit{V}_{\text{on}}$ and the saturation current are degenerated by the decreased Main Gate width. At the reverse conduction, the dual SDM is automatically turned on successively with the increased $\textit{V}_{\text{EC}}$ . For the SDM2, it provides an electron channel and realizes the reverse conduction. For the SDM1, it modulates the electron injection by adjusting the width $\textit{W}_{\text{b}}$ . Thus, the better reverse recovery property is achieved. The results show that the saturation current of SDM-LIGBT with $\textit{W}_{\text{a}}$ : $\textit{W}_{\text{b}}$ of 3:2 is reduced by 68% and the short-circuit tolerance time $\textit{T}_{\text{SC}}$ is extended by 5.1 $\mu$ s compared with the conventional LIGBT. Furthermore, the maximum reverse recovery current $\textit{I}_{\text{rr,max}}$ and time $\textit{T}_{\text{rr}}$ are reduced by 30% and 17% than that of conventional p-i-n diode, respectively.

This study employs monolithic integration technology to fabricate Micro-LED display devices, which present a 0.12-inch, ${640}\times {480}$ blue active-matrix display with an ultra-high pixel density of 6773 pixels per inch (PPI), featuring a pixel size of $1.80~\mu $ m and a pixel pitch of $3.75~\mu $ m. The letter provides a detailed discussion of the fabrication process and the unique design approach used. Our Micro-LED display exhibits a luminance uniformity of 76.00% at 2 A/cm2 and achieves a maximum brightness of 18,720 nits at 3 A/cm2 under full-load conditions. These results demonstrate the tremendous potential of Micro-LED technology for high-resolution near-eye display applications.