This paper reviews architectures and circuit implementations of on-chip sinusoidal signal generators (SSGs) for electrical impedance spectroscopy (EIS) applications. In recent years, there have been increasing interests in on-chip EIS systems, which measure a target material’s impedance spectrum over a frequency range. The on-chip implementation allows EIS systems to have low power and small form factor, enabling various biomedical applications. One of the key building blocks of on-chip EIS systems is on-chip SSG, which determines the frequency range and the analysis precision of the whole EIS system. On-chip SSGs are generally required to have high linearity, wide frequency range, and high power and area efficiency. They are typically composed of three stages in general: waveform generation, linearity enhancement, and current injection. First, a sinusoidal waveform should be generated in SSGs. The generated waveform’s frequency should be accurately adjustable over a wide range. The firstly generated waveform may not be perfectly linear, including unwanted harmonics. In the following linearity-enhancement step, these harmonics are attenuated by using filters typically. As the linearity of the waveform is improved, the precision of the EIS system gets ensured. Lastly, the filtered voltage waveform is now converted to a current by a current driver. Then, the current sinusoidal signal is injected into the target impedance. This review discusses the principles, advantages, and disadvantages of various techniques applied to each step in state-of-the-art on-chip SSGs. In addition, state-of-the-art designs are compared and summarized.

This review article provides a comprehensive overview of impedance-readout integrated circuits (ICs) for electrical impedance spectroscopy (EIS) applications. The readout IC, a crucial component of on-chip EIS systems, significantly affects key performance metrics of the entire system, such as frequency range, power consumption, accuracy, detection range, and throughput. With the growing demand for portable, wearable, and implantable EIS systems in the Internet-of-Things (IoT) era, achieving high energy efficiency while maintaining a wide frequency range, high accuracy, wide dynamic range, and high throughput has become a focus of research. Furthermore, to enhance the miniaturization and convenience of EIS systems, many emerging systems utilize two-electrode or dry electrode configurations instead of the conventional four-electrode configuration with wet electrodes for impedance measurement. In response to these trends, various technologies have been developed to ensure reliable operations even at two- or dry-electrode interfaces. This article reviews the principles, advantages, and disadvantages of techniques employed in state-of-the-art impedance-readout ICs, aiming to achieve high energy efficiency, wide frequency range, high accuracy, wide dynamic range, low noise, high throughput, and/or high input impedance. The thorough review of these advancements will provide valuable insights into the future development of impedance-readout ICs and systems for IoT and biomedical applications.

This paper presents an error-tolerant and power-efficient impedance measurement scheme for bioimpedance acquisition. The proposed architecture measures the magnitude and the real part of the target complex impedance, unlike other impedance measurement architectures measuring either the real/imaginary components or the magnitude and phase. The phase information of the target impedance is obtained by using the ratio between the magnitude and the real components. This can allow for avoiding direct phase measurements, which require fast, power-hungry circuit blocks. A reference resistor is connected in series with the target impedance to compensate for the errors caused by the delay in the sinusoidal signal generator and the amplifier at the front. Moreover, an additional magnitude measurement path is connected to the reference resistor to cancel out the nonlinearity of the proposed system and enhance the settling speed of the low-pass filter by a ratio-based detection. Thanks to this ratio-based detection, the accuracy is enhanced by 30%, and the settling time is improved by 87.7% compared to the conventional single-path detection. The proposed integrated circuit consumes only 513 $\mathsf{\mu }$W for a wide frequency range of 10 Hz to 1 MHz, with the maximum magnitude and phase errors of 0.3% and 2.1$°$, respectively.

In this paper, we present a new impedance measurement integrated circuit (IC) for achieving a wideband coverage up to 10 MHz and low power consumption. A frequency-shift technique is applied to down-shift the input frequency, which ranges from 100 kHz to 10 MHz, into an intermediate frequency of 10 kHz, while the frequency-shifting is bypassed when the input frequency falls in the range from 100 Hz to 100 kHz. It results in 100 times relaxation of the requirement on the instrumentation amplifier (IA) bandwidth and the comparator delay, greatly reducing overall power consumption. The proposed IC employs the polar demodulation structure with a reference resistor that provides reference timing information avoiding any synchronization issue with the transmitter. In order to compensate for the comparator delay and nonlinearity of the IA, the reference magnitude measurement path is added, making only the mismatch of the circuit affects the accuracy. This allows for employing the auto-zeroing technique that can remove the offset but increase the absolute delay by using an additional capacitor to the comparator. The chip fabricated in a 0.18- $\mu$ m CMOS technology consumes the power of 756 $\mu$ W while covering the measurement frequency range from 100 Hz to 10 MHz and exhibiting the maximum magnitude and phase errors of 1.1 $\%$ and 1.9 $^{\circ }$ , respectively.

This paper provides parameter optimization processes of sinusoidal signal generators (SSGs) based on a digital-to-analog converter (DAC) for electrical impedance spectroscopy (EIS) applications. The SSG, which is the most power-hungry building block in EIS systems, generates a sinusoidal signal by using a DAC. To achieve high accuracy for the overall EIS system, high linearity is required for the sinusoidal signal. Thus, the SSG’s DAC is typically operated with a high oversampling ratio (OSR) and a large number of quantization levels ( L_DAC ) at the expense of increased power consumption, large area, and high complexity. For efficient use of the power and area in the SSG, it is necessary to optimize the OSR, L_DAC , and the order of the low-pass filter ( N_LPF ). In this paper, optimal design parameters of SSGs, which can achieve highly accurate EIS systems with low complexity, are presented. First, the minimum OSR and N_LPF for lowering the magnitude error to less than 0.1% are presented. Then, optimal quantization levels of finite-resolution DACs are found for sufficient accuracy and harmonic tones. In addition, the accuracy and harmonics of odd-number OSR cases are analyzed and compared with even-number OSR cases. According to the results, it is possible to design an SSG that only differs from the ideal sinusoidal signal by approximately 0.1% by using OSR ≤ 32, N_LPF ≤ 2, and L_DAC ≤ 256.

This article presents a bio-impedance (bioZ) readout IC featuring a complex-domain noise-correlated baseline cancellation to overcome the limitation of the conventional baseline cancellation with the real-domain noise correlation. The proposed technique is especially beneficial in cases with significant phase shifts between the excitation current from the current generator (CG) and the input voltage signal produced across the bioZ, through which the CG current flows. This technique employs a tunable reference impedance (TRI) and adaptively adjusts it to match the bioZ in both magnitude and phase, thereby achieving a complex-domain correlation of CG noise. By flowing an identical CG current through both the TRI and bioZ, the noise voltages across the TRI and bioZ caused by the CG current become closely correlated with each other, even in the presence of substantial phase shifts, enabling effective CG noise removal after baseline subtraction. Furthermore, this work proposes a differential-difference current-balancing instrumentation amplifier (DD-CBIA) with quiet chopping for baseline subtraction, offering low power consumption, wide input range, and low input-dependent noise. Measurement results demonstrate significant enhancements in noise performance by a factor of 2.47 and 4.88 for the bioZs with phases of 30° and 60°, respectively, achieving a signal-to-noise ratio (SNR) of 101.5 dB and a figure of merit (FoM) of 150.0 dB. Validation through human-subject experiments using two-electrode configurations on the chest and wrist further supports the effectiveness of the proposed bioZ readout IC.