We report on the detailed electrical investigation of all-inkjet-printed thin-film transistor (TFT) arrays focusing on TFT failures and their origins. The TFT arrays were manufactured on flexible polymer substrates in ambient condition without the need for cleanroom environment or inert atmosphere and at a maximum temperature of 150 °C. Alternative manufacturing processes for electronic devices such as inkjet printing suffer from lower accuracy compared to traditional microelectronic manufacturing methods. Furthermore, usually printing methods do not allow the manufacturing of electronic devices with high yield (high number of functional devices). In general, the manufacturing yield is much lower compared to the established conventional manufacturing methods based on lithography. Thus, the focus of this contribution is set on a comprehensive analysis of defective TFTs printed by inkjet technology. Based on root cause analysis, we present the defects by developing failure categories and discuss the reasons for the defects. This procedure identifies failure origins and allows the optimization of the manufacturing resulting finally to a yield improvement.

This paper presents a new family of Class-AB operational transconductance amplifier (OTA) circuits based on single-stage topologies with non-linear current amplifiers. The proposed variable-mirror amplifier (VMA) architecture is mainly characterized by generating all Class-AB current in the output transistors only, by exhibiting very low sensitivity to both technology and temperature deviations, and by avoiding the need for any internal frequency-compensation mechanism. Hence, this family of OTAs is well-suited for low-power switched-capacitor circuits and specifically optimized for switched-OpAmp fast on-off operation and multi-decade load-capacitance specifications. Analytical expressions valid in all regions of operation are presented to minimize VMA settling time in discrete-time circuits. Also, a complete OTA design example integrated in 0.18 μm 1P6M MiM 1.8 V CMOS technology is supplied with detailed simulation and experimental results. Compared to resistor-free state-of-art Class-AB OpAmp and OTA literature, the proposed architecture returns the highest measured figure-of-merit value.

This paper presents a low-power all-MOS delta-sigma ADC specifically optimized for the potentiostatic biasing and amperometric read-out of electrochemical sensors. The proposed architecture reuses the dynamic properties of the sensor itself to implement a continuous-time mixed electrochemical delta-sigma modulator with minimalist analog circuits fully integrable in purely digital CMOS technologies. A 25-μW smart electrochemical sensor demonstrator integrated in low-cost 1M CMOS technology with Au post-processing is presented. Experimental results show electrical dynamic range values exceeding 10-bit, while electrochemical figures exhibit linearity levels close to R² = 0.999 combined with RSD <; 15% in terms of reproducibility. A comparative test with commercial potentiostat equipment is also included to qualify the performance of the proposed ADC.

Application specific printed electronic circuits (ASPECs) are the corresponding term with application-specified ICs for printed electronics. The same as any new technology, printed electronics is suffering from some restrictions in design and process technology aspects. An important stage in the ASPEC design is the final wiring of the organic thin-film transistor arrays or gate arrays to customize it to implement any specific target application that fits in their structure. In this paper, we evaluate two additive manufacturing technologies: aerosol jet using Optomec M3D and electrohydrodynamic printer using superfine inkjet. Both techniques are based on direct-writing of the pattern corresponding to any individual circuit being fabricated (digital printing) enabled by the mask-free noncontact deposition of materials. Finally, these structures will be compared with the corresponding photolithography mask technology. Some parameterized test vehicles, with different instantiations for the variation of line widths and separations, have been designed to be wired using the target technologies. These test vehicles have been fabricated at the Centre for Process Innovation by a five masks lithography and subtractive patterning technology. Results show that both direct printing technologies are feasible for the fabrication of the gate-array customization, thus allowing individual personalization of every circuit what can produce added value functionalities at low cost such as the equivalent effect of having an ROM memory which final contents could be customized at home by using low-cost digital printing technologies. Further interactions between transistor bulk and wiring technologies can improve the obtained performance in order to end up in an industrialized process.