An electrical characterization of ${\mathrm{Al}}_2{\mathrm{O}}_3$ based metal-insulator-semiconductor structures has been carried out by using capacitance-voltage, deep level transient spectroscopy, and conductance-transient $\left(G\text{-}t\right)$ techniques. Dielectric films were atomic layer deposited (ALD) at temperatures ranging from 300 to 800 °C directly on silicon substrates and on an ${\mathrm{Al}}_2{\mathrm{O}}_3$ buffer layer that was grown in the same process by using 15 ALD cycles at 300 °C. As for single growth temperatures, 300 °C leads to the lowest density of states distributed away from the interface to the insulator [disorder-induced gap states (DIGS)], but to the highest interfacial state density $\left(D_{\mathrm{it}}\right)$ . However, by using $300∕500°\mathrm{C}$ double growth temperatures it is possible to maintain low DIGS values and to improve the interface quality in terms of $D_{\mathrm{it}}$ . The very first ALD cycles define the dielectric properties very near to the dielectric-semiconductor interface, and growing an upper layer at higher ALD temperature produces some annealing of interfacial states, thus improving the interface quality. Also, samples in which the only layer or the upper one was grown at the highest temperature (800 °C) show the poorest results both in terms of $D_{\mathrm{it}}$ and DIGS, so using very high temperatures yield defective dielectric films.

Intermediate band formation on silicon layers for solar cell applications was achieved by titanium implantation and laser annealing. A two-layer heterogeneous system, formed by the implanted layer and by the un-implanted substrate, was formed. In this work, we present for the first time electrical characterization results which show that recombination is suppressed when the Ti concentration is high enough to overcome the Mott limit, in agreement with the intermediate band theory. Clear differences have been observed between samples implanted with doses under or over the Mott limit. Samples implanted under the Mott limit have capacitance values much lower than the un-implanted ones as corresponds to a highly doped semiconductor Schottky junction. However, when the Mott limit is surpassed, the samples have much higher capacitance, revealing that the intermediate band is formed. The capacitance increasing is due to the big amount of charge trapped at the intermediate band, even at low temperatures. Ti deep levels have been measured by admittance spectroscopy. These deep levels are located at energies which vary from 0.20 to 0.28 eV below the conduction band for implantation doses in the range 10¹³-10¹⁴ at./cm². For doses over the Mott limit, the implanted atoms become nonrecombinant. Capacitance voltage transient technique measurements prove that the fabricated devices consist of two-layers, in which the implanted layer and the substrate behave as an n⁺/n junction.

A crucial step in order to achieve fast and low-energy switching operations in resistive random access memory (RRAM) memories is the reduction of the programming pulse width. In this study, the incremental step pulse with verify algorithm (ISPVA) was implemented by using different pulse widths between 10 $\mathsf{\mu }$ s and 50 ns and assessed on Al-doped HfO ${}_2$ 4 kbit RRAM memory arrays. The switching stability was assessed by means of an endurance test of 1k cycles. Both conductive levels and voltages needed for switching showed a remarkable good behavior along 1k reset/set cycles regardless the programming pulse width implemented. Nevertheless, the distributions of voltages as well as the amount of energy required to carry out the switching operations were definitely affected by the value of the pulse width. In addition, the data retention was evaluated after the endurance analysis by annealing the RRAM devices at 150 °C along 100 h. Just an almost negligible increase on the rate of degradation of about 1 $\mathsf{\mu }$ A at the end of the 100 h of annealing was reported between those samples programmed by employing a pulse width of 10 $\mathsf{\mu }$ s and those employing 50 ns. Finally, an endurance performance of 200k cycles without any degradation was achieved on 128 RRAM devices by using programming pulses of 100 ns width.