Counterfeit electronic devices can cause a significant revenue loss and brand value damage to the original component manufacturers (OCM). In addition, they can instigate serious safety and security issues in critical military and space applications. These devices can be injected by untrusted entities in the supply chain, such as outsourced foundries, distributors, PCB assemblers, and system integrators. Existing methods for device authenticity verification are either destructive, require an advanced electrical test or physical inspection infrastructure. Furthermore, the existing database query-based verification systems by OCMs provide an illusion of authenticity verification by looking for a device record in their online system. In reality, a customer may have bought a cloned or recycled copy of an electronic device and may find a valid record in the OCM verification system. This paper presents a blockchain-centric solution to address these limitations to verify electronic devices. A detailed study is presented to transform an existing supply chain into a trustworthy distributed ledger framework called eChain (electronic Chain). eChain generates device provenance records from blockchain that users can utilize to classify authentic and counterfeit ICs. A fully functional prototype of eChain is developed to demonstrate the feasibility and efficacy of the proposed solution.

Hardware Trojans are malicious modifications in integrated circuits (ICs) with an intent to breach security and compromise the reliability of an electronic system. This article proposes a framework using self-testing, advanced imaging, and image processing with machine learning to detect hardware Trojans inserted by untrusted foundries. It includes on-chip test structures with negligible power, delay, and silicon area overheads. The core step of the framework is on-chip golden circuit design, which can provide authentic samples for image-based Trojan detection through self-testing. This core step enables a golden-chip-free Trojan detection that does not rely on an existing image data set from Trojan-free chip or image synthesizing. We have conducted an in-depth analysis of detection steps and discussed possible attacks with countermeasures to strengthen this framework. The performance evaluation on a 28-nm FPGA and a 90-nm IC validates its high accuracy and reliability for practical applications.

Heterogeneous integration (HI) of chiplets provides benefits of diverse functionality, high performance with compact packaging. These chiplets can be assembled and interconnected on a packaging substrate to build a system-in-package (SiP) by a supply chain entity called SiP designer / OEM. Furthermore, the involvement of an overseas pure-play untrusted foundry and various chiplet suppliers may cause an increased number of potentially untrusted chiplets in the supply chain. These foundries have complete access to the GDSII layout and test vectors. As a result, an adversarial foundry can perform malicious changes (hardware Trojans) in chiplets, exposing respective SiP to security attacks. For a secure heterogeneous integration, all chiplets need trust validation by the SiP designer. The trust validation of these chiplets can be challenging as SiP designers do not have access to proprietary information such as chiplet layout and test vectors. This paper proposes a physical inspection-based semiconductor certification authority (SeCA) for trust validation of chiplets. SeCA will perform the trust validation of chiplets by getting minimal information from the chiplet design house or OEM. The chiplet design house will facilitate trust validation by sharing the image of the active region of transistors from the chiplet layout. This minimal information protects the chiplet design house from IP theft, and it will be used to compare with the backside SEM image of chiplets shared by SiP designers to detect any malicious change. We have validated our proposed approach using an active layer layout image and corresponding SEM image of an IC and demonstrated malicious change detection in various scenarios.

Due to the ever-growing demands for electronic chips in different sectors, semiconductor companies have been mandated to offshore their manufacturing processes. This unwanted matter has made security and trustworthiness of their fabricated chips concerning and has caused the creation of hardware attacks. In this condition, different entities in the semiconductor supply chain can act maliciously and execute an attack on the design computing layers, from devices to systems. Our attack is a hardware Trojan that is inserted during mask generation/fabrication in an untrusted foundry. The Trojan leaves a footprint in the fabrication through addition, deletion, or change of design cells. To tackle this problem, we propose EVHA (Explainable Vision System for Hardware Testing and Assurance) in this work, which can detect the smallest possible change to a design in a low-cost, accurate, and fast manner. The inputs to this system are scanning electron microscopy images acquired from the integrated circuits under examination. The system output is the determination of integrated circuit status in terms of having any defect and/or hardware Trojan through addition, deletion, or change in the design cells at the cell level. This article provides an overview on the design, development, implementation, and analysis of our defense system.