The capability of multiple valued logic (MVL) circuits to achieve higher storage density when compared to that of existing binary circuits is highly impressive. Recently, MVL circuits have attracted significant attention for the design of digital systems. Carbon nanotube field effect transistors (CNTFETs) have shown great promise for design of MVL based circuits, due to the fact that the scalable threshold voltage of CNTFETs can be utilized easily for the multiple voltage designs. In addition, resistive random access memory (RRAM) is also a feasible option for the design of MVL circuits, owing to its multilevel cell capability that enables the storage of multiple resistance states within a single cell. In this manuscript, a design approach for ternary combinational logic circuits while using CNTFETs and RRAM is presented. The designs of ternary half adder, ternary half subtractor, ternary full adder, and ternary full subtractor are evaluated while using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions, including different supply voltages, output load variation, and different operating temperatures. Finally, the proposed designs are compared with the state-of-the-art ternary designs. Based on the obtained simulation results, the proposed designs show a significant reduction in the transistor count, decreased cell area, and lower power consumption. In addition, due to the participation of RRAM, the proposed designs have advantages in terms of non-volatility.

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Epileptic seizures impair patients’ health and quality of life, and electroencephalography (EEG)-based prediction enables timely intervention. Early work on epileptic seizure prediction employed linear models, whereas recent studies employ more advanced machine learning and deep learning models. We review 149 studies (2018—May 2025), summarizing trends and gaps across the full pipeline in EEG-based epileptic seizure prediction. We find that four persistent challenges related to this domain remain. First, severe dataset imbalance, with overreliance on Children’s Hospital Boston–Massachusetts Institute of Technology EEG dataset (CHB-MIT), minimal use of intracranial electroencephalography (iEEG) datasets, and infrequent integration of public and private datasets. Second, preprocessing practices remain rigid, often involving segmentation into windows of 10 s or less, fixed preictal horizons of 30 to 60 min, basic filtering and undersampling procedures. Third, limited model diversity, as most studies use convolutional neural networks (CNNs), with scant exploration of Transformers or graph neural networks (GNNs), dimensionality reduction is predominantly implicit and few linear baselines. Fourth, validation and deployment are fragmented, with fixed warning horizons, single evaluation protocols, missing clinical metrics, static thresholds or k-of-n voting, minimal interpretability, and few real-world implementations. Future work should assemble heterogeneous EEG datasets, adopt adaptive multiscale preprocessing, and build unified benchmarks that pit CNN, Transformer, GNN, and related models against well-tuned linear baselines—advancing flexible non-convolutional designs beyond the time-frequency paradigm, mandating ablations that contrast implicit with explicit, task-aware dimensionality reduction, and pairing these evaluations with clinically aligned validation, dynamic risk-aware thresholds, embedded interpretability, and prospective testing on energy-efficient edge hardware in ward and home settings.

This paper presents a nonscan design-for-testability (DFT) method for register-transfer-level (RTL) circuits. We first introduce the notation to analyze the test generation complexity, as well as two classes of sequential circuits, namely: 1) the combinationally testable class and 2) the acyclically testable class. Then, we introduce a new class of linear-depth time-bounded circuits as one of the acyclically testable classes. The linear-depth time-bounded testability guarantees that the number of time frames required for any testable fault is bounded by a linear function of the number of flip-flops in the circuit during the test generation process. As one of the linear-depth time-bounded classes, we introduce a new class of RTL circuits, called the cycle-unrollable RTL circuits, which is shown to be linear depth time bounded. We propose a DFT method to make RTL circuits cycle unrollable and a test generation method for cycle-unrollable RTL circuits. Experimental results show that we can drastically reduce hardware overhead and test application time compared to the full-scan method and the method proposed by Ohtake Moreover, our proposed method can achieve 100% fault efficiency for gate-level single stuck-at faults in practical test generation time and allow at-speed testing.

Test power has been turned to a bottleneck for test considerations as the excessive power dissipation has serious negative effects on chip reliability. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption but also introduce spurious switching activities in the combinational logic. In this paper, we propose a novel area-efficient gating scan architecture that offers an integrated solution for reducing total average power in both scan cells and combinational part during shift mode. In the proposed gating scan structure, conventional master/slave scan flip-flop has been modified into a new gating scan cell augmented with state preserving and gating logic that enables average power reduction in combinational logic during shift mode. The new gating scan cells also mitigate the number of transitions during shift and capture cycles. Thus, it contributes to average power reduction inside the scan cell during scan shifting with low impact on peak power during capture cycle. Simulation results have shown that the proposed gating scan cell saves 28.17% total average power compared to conventional scan cell that has no gating logic and up to 44.79% compared to one of the most common existing gating architectures.