In recent years, because of stringent needs in the fabrication of silicon carbide (SiC) power devices, laser annealing has been introduced to achieve local ohmic contact. In this paper, the laser annealing research for the ohmic contact process of SiC power devices is reviewed, which is mainly divided into four aspects: laser process mechanism, ohmic contact electrode materials, and substrate materials. The effect of laser parameters on ohmic contact and the annealing process on SiC diode devices is also reviewed. Progress of other substrate materials, namely 6H-SiC and semi-insulating 4H-SiC-based devices with laser annealed ohmic contacts, is also briefly discussed, in which formation of semi-insulating SiC ohmic contacts is derived from laser irradiation at the interface to produce 3C-SiC. Some experiment results have been shown in the passage, such as XRD, SEM, TEM, etc. In the review, it points out that the direction of application and development of the laser annealing process for improving the ohmic contact of SiC power devices is highly encouraging.

With more than thirty years of research and development until commercialization, performance, reliability, and robustness of silicon carbide (SiC) based devices have been improved significantly due to drastic reduction in crystal defects from the well-controlled processes of crystal growth and device fabrication. It is crucial to investigate the effects of SiC crystal defects on the electrical characteristics of devices. Here, an up-to-date development of the correlation between crystal defects of SiC with electrical performance of the devices has been reviewed. The effect of defects on the electrical parameters of the device and the failure mechanism are discussed, and the development of SiC in recent years is prospected.

A novel cell topology for a vertical 1200 V SiC planar double-implanted MOSFET (DMOSFET) is proposed in this work. Based on the conventional linear cell topology and the calibrated two-dimensional (2D) technology computer-aided design (TCAD) model parameters, a novel cell topology with the insertion of P+ body implanted regions over a fractional part of the channel and junction field effect transistor (JFET) regions was designed and optimized to achieve a low high-frequency figure of merit (HF-FOM, R_on × C_gd). Utilizing three-dimensional (3D) TCAD simulations, the new proposed cell topology with optimized selected structure parameters exhibits an HF-FOM of 328.748 mΩ·pF, which is 10.02% lower than the conventional linear topology. It also shows an improvement in the switching performance, with an 11.73% reduction in switching loss. Moreover, the impact of source ohmic contact resistivity on the performance of the proposed cell topology was highlighted, indicating the dependency of the source ohmic contact resistivity on the switching performance. This research provides a new perspective for enhancing the switching performance of SiC MOSFETs in high-frequency applications, considering practical factors such as contact resistivity.

In this paper, a ∼2 nm in situ SiN cap layer on AlGaN barrier layer is grown, which is revealed to be crystalline using high-resolution cross-sectional transmission electron microscopy. Benefitting from superior interface quality of epitaxial crystalline SiN/AlGaN interface, the gate diodes with in situ SiN cap layer feature lower interface trap state density than that with GaN cap layer. By comparing the GaN high electron mobility transistors (HEMTs) with the conventional GaN cap layer, the GaN HEMTs with in situ SiN cap layer exhibit improved device performance, showing higher electron mobility, higher drain current, larger on/off current ratio, and higher transconductance. For breakdown characteristics, the devices with in situ crystalline SiN cap layer show prominent advantages over the GaN cap layer with a 30% breakdown voltage increase to 810 V.