The SiC MOSFET with an integrated SBD (SBD-MOSFET) exhibits excellent performance in power electronics. However, the static and dynamic characteristics of this device are influenced by a multitude of parameters, and traditional TCAD simulation methods are often characterized by their complexity. Due to the increasing research on neural networks in recent years, such as the application of neural networks to the prediction of GaN JBS and Finfet devices, this paper considers the application of neural networks to the performance prediction of SiC MOSFET devices with an integrated SBD. This study introduces a novel approach utilizing neural network machine learning to predict the static and dynamic characteristics of the SBD-MOSFET. In this research, SBD-MOSFET devices are modeled and simulated using Sentaurus TCAD(2017) software, resulting in the generation of 625 sets of device structure and sample data, which serve as the sample set for the neural network. These input variables are then fed into the neural network for prediction. The findings indicate that the mean square error (MSE) values for the threshold voltage (Vth), breakdown voltage (BV), specific on-resistance (R_on), and total switching power dissipation (E) are 0.0051, 0.0031, 0.0065, and 0.0220, respectively, demonstrating a high degree of accuracy in the predicted values. Meanwhile, in the comparison of convolutional neural networks and machine learning, the CNN accuracy is much higher than the machine learning methods. This method of predicting device performance via neural networks offers a rapid means of designing SBD-MOSFETs with specified performance targets, thereby presenting significant advantages in accelerating research on SBD-MOSFET performance prediction.

A novel cell topology for a vertical 1200 V SiC planar double-implanted MOSFET (DMOSFET) is proposed in this work. Based on the conventional linear cell topology and the calibrated two-dimensional (2D) technology computer-aided design (TCAD) model parameters, a novel cell topology with the insertion of P+ body implanted regions over a fractional part of the channel and junction field effect transistor (JFET) regions was designed and optimized to achieve a low high-frequency figure of merit (HF-FOM, R_on × C_gd). Utilizing three-dimensional (3D) TCAD simulations, the new proposed cell topology with optimized selected structure parameters exhibits an HF-FOM of 328.748 mΩ·pF, which is 10.02% lower than the conventional linear topology. It also shows an improvement in the switching performance, with an 11.73% reduction in switching loss. Moreover, the impact of source ohmic contact resistivity on the performance of the proposed cell topology was highlighted, indicating the dependency of the source ohmic contact resistivity on the switching performance. This research provides a new perspective for enhancing the switching performance of SiC MOSFETs in high-frequency applications, considering practical factors such as contact resistivity.

A SiC fin-channel MOSFET structure (Fin-MOS) is proposed for an enhanced gate shielding effect. The gates are placed on each side of the narrow fin-channel region, while grounded p-shield regions below the gates provide a strong shielding effect. The device is investigated using Sentaurus TCAD. For a narrow fin-channel region, there is difficulty in forming an Ohmic contact to the p-base; a floating p-base might potentially store negative charges upon high drain voltage, and, thus, causes threshold voltage instabilities. The simulation reveals that, for a fin-width of 0.2 μm, the p-shield regions provide a stringent shielding effect against high drain voltage, and the dynamic threshold voltage shift (∆V_th) is negligible. Compared to conventional trench MOSFET (Trench-MOS) and asymmetric trench MOSFET (Asym-MOS), the proposed Fin-MOS boasts the lowest OFF-state oxide field and reverse transfer capacitance (C_rss), while maintaining a similar low ON-resistance.

Surge reliability is a crucial aspect of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) reliability. This study investigates the degradation behavior and mechanisms of switching characteristics in 1.2 kV planar-gate SiC MOSFETs under repetitive surge current. A surge current test platform is established to conduct surge tests on the device, while monitoring the evolution of its switching characteristics. The results indicate that after 4000 surge current cycles, the device’s turn-on delay time (t_d(on)), rise time (t_r), and turn-on loss (E_ON) show no significant changes. In contrast, the turn-off delay time (t_d(off)), fall time (t_f), and turn-off loss (E_OFF) increase by 9%, 7.5%, and 8.3%, respectively. Switching characteristics variations are closely linked to the reduction in threshold voltage (V_TH) and the increase in gate-source capacitance (C_GS) and gate-drain capacitance (C_GD). The degradation of these parameters stems from the accumulation of positive trapped charge in the gate oxide layer above the channel and junction field-effect transistor (JFET) region. The increase in charges results from the combined effects of negative gate bias and cyclic high temperature induced by repetitive surge current. This study provides a theoretical basis for the comprehensive understanding of the impact of surge current on SiC MOSFET performance.