We report the demonstration of growing two-dimensional (2D) hexagonal-AlN (h-AlN) on transition metal dichalcogenide (TMD) monolayers (MoS₂, WS₂, and WSe₂) via van der Waals epitaxy by atomic layer deposition (ALD). Having atomically thin thickness and high theoretical carrier mobility, TMDs are attractive semiconductors for future dense and high-performance 3D IC, and 2D hexagonal boron nitride (h-BN) as a gate dielectric is known to significantly improve TMD device performance. However, h-BN growth requires 1000 °C temperature that is not compatible with CMOS fabrication, and ALD deposition of any high-k 2D insulator on TMD continues to be an elusive goal. The epitaxial 2D layered h-AlN by low-temperature ALD is characterized by synchrotron-based grazing-incidence wide-angle x-ray scattering and high-resolution transmission electron microscopy. In addition, we demonstrate the feasibility of using layered h-AlN as an interfacial layer between WS₂ and ALD HfO₂. The significantly better uniformity and smoothness of HfO₂ than that directly deposited on TMD are desirable characteristics for TMD transistor applications.

Single-phase two-dimensional (2D) indium monoselenide (γ-InSe) film is successfully grown via solid phase epitaxy in the molecular beam epitaxy (MBE) system. Having high electron mobility and high photoresponsivity, ultrathin 2D γ-InSe semiconductors are attractive for future field-effect transistor and optoelectronic devices. However, growing single-phase γ-InSe film is a challenge due to the polymorphic nature of indium selenide (γ-InSe, α-In₂Se₃, β-In₂Se₃, γ-In₂Se₃, etc.). In this work, the 2D α-In₂Se₃ film was first grown on a sapphire substrate by MBE. Then, the high In/Se ratio sources were deposited on the α-In₂Se₃ surface, and an γ-InSe crystal emerged via solid-phase epitaxy. After 50 min of deposition, the initially 2D α-In₂Se₃ phase was also transformed into a 2D γ-InSe crystal. The phase transition from 2D α-In₂Se₃ to γ-InSe was confirmed by Raman, XRD, and TEM analysis. The structural ordering of 2D γ-InSe film was characterized by synchrotron-based grazing-incidence wide-angle X-ray scattering (GIWAXS).

In this letter, we have successfully fabricated a metal-ferroelectricity-metal (MFM) capacitor of an ultrathin 5.6 nm HZO and ultrathin In₂O₃ back gate devices in a back-end-of-line (BEOL) compatible process. By proposing a novel atomic layer deposition (ALD) scheme and an alternative bottom electrode treatment, the MoN-HZO sample shows an average 2Pr value of 64 $\mu$C/cm² (with a standard deviation of 0.52) and high endurance ($\Delta \, 2\rm {Pr}/2\rm {Pr}_\rm {pristine} \approx 2\, \%$ from pristine to 10¹⁰ cycles). The MoN.HZO stack integrated with an ultrathin In₂O₃ back gate exhibits a memory window (MW) greater than 2.5 V and excellent endurance and data retention characteristics. With a maximum process temperature of 400 $^{\circ }$C, our approach meets the stringent requirements for Back-End-of-Line (BEOL) integration.

Dual-gate (DG) WSe₂ field-effect transistors (FETs) offer superior electrostatic control and scaling potential compared to conventional back-gate (BG) devices, yet their practical implementation remains limited by the challenge of integrating ultrathin, high-quality gate dielectrics without damaging the 2-D channel. This work presents a CMOS-compatible, low-temperature ( $100^{\circ }$ C) plasma-enhanced atomic layer deposition (PE-ALD) strategy employing aluminum nitride (AlN) as an interface-nucleation layer, followed by thermally grown hafnium dioxide (TH-HfO ${}_{{2}}\text {)}$ , to realize a top-gate dielectric stack with an equivalent oxide thickness (EOT) below 1 nm. Optimizing the AlN deposition power to 100 W yields the smoothest surface, lowest roughness, and best crystallinity, as confirmed by Raman spectroscopy, atomic force microscopy, and X-ray diffraction (XRD). Electrical characterization under DG operation demonstrates excellent gate modulation, reduced hysteresis, and enhanced drive current, with the 100-W condition achieving the highest drain current of $4.66\,\times\, 10^{-{5}}$ A/ $\mu $ m post-deposition annealing. These results highlight a scalable, low-power pathway for integrating high-performance dielectrics with 2-D semiconductors, enabling future nanoelectronic and optoelectronic applications.