In this paper, we propose to study voltage controlled oscillators (VCOs) based on the equivalence with pulse frequency modulators (PFMs). This approach is applied to the analysis of VCO-based analog-to-digital converters (VCO-ADCs) and deviates significantly from the conventional interpretation, where VCO-ADCs have been described as the first-order ΔΣ modulators. A first advantage of our approach is that it unveils systematic error components not described by the equivalence with a conventional ΔΣ modulator. A second advantage is that, by a proper selection of the pulses generated by the PFM, we can theoretically construct an open loop VCO-ADC with an arbitrary noise shaping order. Unfortunately, with the exception of the first-order noise shaping case, the required pulse waveforms cannot easily be implemented on the circuit level. However, we describe circuit techniques to achieve a good approximation of the required pulse waveforms, which can easily be implemented by practical circuits. Finally, our approach enables a straightforward description of multistage ΔΣ modulator architectures, which is an alternative and practically feasible way to realize a VCO-ADC with extended noise shaping.

In this work, we focus on the three most relevant pseudo-digital ring oscillator circuits for VCO A/D conversion. First, we show that they can be accurately modeled by an equivalent 2-terminal diode-like element. Next, we study the main analog performance figures: the effective oscillation frequency (which affects the quantization noise of a VCO ADC), the input referred noise and the power efficiency both for voltage and current control. We do this both through theoretical modeling as well as through simulations, which are in good agreement with each other. Our study highlights several important independencies: e.g. most performance metrics are independent on the number of VCO stages and the external load capacitance on the VCO nodes. In contrast to these independencies, we identify several important dependencies. In particular, we show that the biasing of the ring has an enormous impact on power efficiency of the ring. This dependency is different for the case of a voltage- or current mode configuration of the ring.

Recently an extremely linear voltage‐controlled ring‐oscillator for use in VCO‐ADCs was proposed by Babaie‐Fishani and Rombouts. In this current Letter, a circuit‐level technique to improve the bandwidth and noise performance of such a linear VCO is proposed. The key element is the modified delay cell, where the traditional cross‐coupled inverters are modified into ‘feed‐forward’ coupling inverters that pre‐charge the subsequent elements in the ring. The resulting circuit maintains the excellent linearity, but has greatly enhanced bandwidth (up to 3 times higher) and considerably reduced power for the same circuit noise level (up to 2.5 times lower).

The upcoming 100 Gb/s links in the next-generation ethernet passive optical networks will be based on four channels of 25 Gb/s. The corresponding transceivers in these optical links require a high-speed clock and data recovery circuit to extract a synchronous clock and recover the received data. To achieve a sufficiently fast settling time for 25 Gb/s burst mode upstream applications in passive optical networks (PONs), we introduce an architecture of the first 25 Gb/s all-digital clock and data recovery circuit (AD-CDR). Thanks to the implementation of a digital loop filter, our AD-CDR avoids the need of a system clock or a start-of-burst signal. This circuit is implemented in a 40-nm CMOS process and has a very compact active chip area of only 0.050 mm ² . Furthermore, the performance of the burst-mode operation of our AD-CDR in an optical setup is measured and reported, resulting in a burst-mode lock time of 37.5 ns and consuming only 46 mW.

Recently, there has been a strong drive to replace established analog circuits for multi-gigabit clock and data recovery (CDR) by more digital solutions. We focused on phase locked loop-based all-digital CDR (AD-CDR) techniques which contain a digital loop filter (DLF) and a digital controlled oscillator (DCO) and pushed the digital integration up to a level where our DLF is entirely synthesized. To enable this, we found that extensive subsampling can be used to decrease the speed of the DLF while maintaining a good operation. Additionally, an Inverse Alexander phase detector and a 5.5-bit resolution DCO complete the AD-CDR architecture. As a result of the low complexity and digital architecture, the AD-CDR occupies a compact active chip area of 0.050 mm ² and consumes only 46 mW at 25 Gb/s. This is the smallest area and the lowest power consumption compared with the state-of-the-art. In addition, our implementation is highly tunable due to the synthesized logic, and supports a wide operating range (12.5-25 Gb/s), which is a significantly larger range compared with the previous work. Finally, thanks to our digital architecture, the power dissipation decreases linearly while moving to the lower speeds of our operating range. This is in contrast with the most prior work, making our design truly adaptive.

For the design of ring oscillator-based ADCs, little has been reported on how to optimally co-design the readout scheme and the ring oscillator core towards optimal energy efficiency. This paper describes a methodology to find this optimum for a target SQNR and signal bandwidth, for the case of 1 ^st -order quantization noise shaping. In short, starting from initial assumptions on the VCO, the readout optimization boils down to finding the best VCO frequency. From this, the number of readout phases, the sampling frequency of the readout and the number of bits in the quantizers are derived. Then, it is explained how to adjust the VCO core toward the corresponding optimal VCO configuration. This is discussed for the case of a current-controlled ring oscillator, indicating the main constraints that define the design space for such a VCO optimization. If the actual VCO configuration is bounded by practical constraints, this approach can be re-iterated where a new readout optimization is performed taking these constraints into account.