The behavior of silicon carbide (SiC) power MOSFETs under stressful short-circuit (SC) conditions is investigated in this paper. Two different SC failure phenomena for SiC power MOSFETs are thoroughly reported. Experimental evidence and TCAD electrothermal simulations are exploited to describe and discriminate the failure sources. Physical causes are finally investigated and explained by means of properly calibrated numerical investigations and are reported along with their effects on devices' SC capability.

SND@LHC is a compact and stand-alone experiment designed to perform measurements with neutrinos produced at the LHC in the pseudo-rapidity region of 7.2 < η < 8.4. The experiment is located 480 m downstream of the ATLAS interaction point, in the TI18 tunnel. The detector is composed of a hybrid system based on an 830 kg target made of tungsten plates, interleaved with emulsion and electronic trackers, also acting as an electromagnetic calorimeter, and followed by a hadronic calorimeter and a muon identification system. The detector is able to distinguish interactions of all three neutrino flavours, which allows probing the physics of heavy flavour production at the LHC in the very forward region. This region is of particular interest for future circular colliders and for very high energy astrophysical neutrino experiments. The detector is also able to search for the scattering of Feebly Interacting Particles. In its first phase, the detector is ready to operate throughout LHC Run 3 and collect a total of 250 fb^-1.

Failure mechanisms during short-circuit conditions of Silicon Carbide Power MOSFETs are analysed in this work, and a possible theoretical explanation is provided. Insight into the physics involved in such processes was inferred through experimental and numerical analyses. The TCAD structure used for electro-thermal simulations was calibrated to fit the I_D-V_GS characteristics of a commercial device. Adequate physical effects were considered, such as the presence of charges and traps at the oxide-SiC interface and their effect on threshold voltage and carrier mobility. Experimental evidences were explained by analyzing the numerical results. The high temperature reached during these operating conditions was addressed as the main cause of the device failure. The effect on the leakage current and the activation of a parasitic bipolar transistor are also shown.

This paper presents a temperature-dependent SPICE model for SiC power MOSFETs. The model describes the static and dynamic behavior and accounts for leakage current and impact ionization. The technology-dependent MOSFET parameters are extracted from characterization measurements and datasheets. SPICE standard components and analog behavior modeling blocks are adopted for the model implementation. The model ensures a good agreement with experimental data over a wide temperature range, even under out-of-safe-operating-area conditions close to the failure occurrence.

The physics of the different failure modes that limit the maximum avalanche capability during unclamped inductive switching (UIS) in punchthrough (PT) and not PT (NPT) insulated-gate bipolar transistor (IGBT) structures is analyzed in this paper. Both 3-D electrothermal numerical simulations and experimental evaluations support the theoretical analysis. Experimental results for UIS test show that, at low time duration (or inductance value) of the test, the UIS limit moves from energy limitation to current limitation. While the energy limitation is well known, the current-limited failures are less studied. In this paper, the current limit for UIS test is analyzed in detail, and the cause is attributed to a filamentary current conduction due to the presence of a negative differential resistance (NDR) region in the I_C- V_CE curve in breakdown. The filamentary current conduction locally increases the current density causing early device latch-up and possible device failure at a current much lower than the one dictated by energy limitations. The physical parameters that affect both the onset of NDR region and the failure current are discussed for both an NPT trench IGBT structure with a local lifetime control and a PT trench IGBT structure with a field-stop layer.