The behavior of silicon carbide (SiC) power MOSFETs under stressful short-circuit (SC) conditions is investigated in this paper. Two different SC failure phenomena for SiC power MOSFETs are thoroughly reported. Experimental evidence and TCAD electrothermal simulations are exploited to describe and discriminate the failure sources. Physical causes are finally investigated and explained by means of properly calibrated numerical investigations and are reported along with their effects on devices' SC capability.

This paper presents a temperature-dependent SPICE model for SiC power MOSFETs. The model describes the static and dynamic behavior and accounts for leakage current and impact ionization. The technology-dependent MOSFET parameters are extracted from characterization measurements and datasheets. SPICE standard components and analog behavior modeling blocks are adopted for the model implementation. The model ensures a good agreement with experimental data over a wide temperature range, even under out-of-safe-operating-area conditions close to the failure occurrence.

This paper presents an in-depth investigation into the avalanche breakdown robustness of commercial state-of-the-art silicon carbide (SiC) power MOSFETs comprising of functional as well as structural characterization and the corresponding underlying physical mechanisms responsible for device failure. One aspect of robustness for power MOSFETs is determined by its ability to withstand energy during avalanche breakdown. Avalanche energy (E_AV) is an important figure of merit for all applications requiring load dumping and/or to benefit from snubber-less converter design. 2D TCAD electro-thermal simulations were performed to get important insight into the failure mechanism of SiC power MOSFETs during avalanche breakdown.

In this study, an electrothermal compact model for SiC power MOSFETs is experimentally verified for the first time on a 3.3 kV device. Both the parameters determining the static behavior and those controlling the dynamic performances are calibrated over experimental data. The good agreement achieved proves the model scalability form 1.2 kV devices to 3.3 kV ones. Successively, to validate the good convergence properties of the model, an electrothermal simulation of a three-phase inverter consisting of 36 hard switched MOSFETs is performed.

Silicon power diodes are used to design different types of electrical energy systems. Their performance has been improved substantially, as a result of a concentrated research efforts that have taken place in the last two decades. They are considered immune to electrostatic discharge (ESD) failures, since usually they withstand an avalanche energy one order of magnitude higher than that of the ESD. Consequently, few works consider this aspect. However, it was observed that during the mounting of power diodes in automotive systems (e.g., with operators touching and handling the devices), ESD events occur and devices fail. In this paper the ESD capability of 600 V fast recovery epitaxial diode (FRED) is analyzed by means of Technology Computer-Aided Design (TCAD) simulations, theoretical analyses and experimental characterization. Two doping profiles are investigated in order to improve the ESD robustness of a standard device and an optimized doping profile is proposed. The proposed design exhibits a higher ESD robustness and this is due to its superior capability in keeping the current distribution uniform in the structure in a critical condition such as the impact ionization avalanche effect. Both experimental and numerical results validate the proposed design.