An 8 × 16 pixel array based on CMOS small-area silicon photomultipliers (mini-SiPMs) detectors for PET applications is reported. Each pixel is 570 × 610 μm² in size and contains four digital mini-SiPMs, for a total of 720 SPADs, resulting in a full chip fill-factor of 35.7%. For each gamma detection, the pixel provides the total detected energy and a timestamp, obtained through two 7-b counters and two 12-b 64-ps TDCs. An adder tree overlaid on top of the pixel array sums the sensor total counts at up to 100 Msamples/s, which are then used for detecting the asynchronous gamma events on-chip, while also being output in real-time. Characterization of gamma detection performance with an 3 × 3 × 5 mm³ LYSO scintillator at 20°C is reported, showing a 511-keV gamma energy resolution of 10.9% and a coincidence timing resolution of 399 ps.

The Abbe–Rayleigh diffraction limit constrains spatial resolution for classical imaging methods. Quantum imaging exploits correlations between photons to reproduce structures with higher resolution. Quantum-correlated $N$-photon states were shown to potentially surpass the classical limit by a factor of $1/N$, corresponding to the Heisenberg limit, using a method known as optical centroid measurement (OCM). In this work, the theory of OCM is reformulated for its application in imaging. Using entangled photon pairs and a recently developed integrated time-resolving detector array, OCM is implemented in a proof-of-principle experiment that demonstrates the expected enhancement. Those results show the relevance of entanglement for imaging at the Heisenberg limit.

A single-photon, time-gated, 160 × 120 pixel imager is presented for its application in fluorescence lifetime imaging microscopy. Exploiting single-photon avalanche diodes and an extremely compact pixel circuitry-only seven MOSFETs and one MOSCAP-the imager is capable of gathering information about photon position, number, and time distribution, enabling cost-effective devices for scientific imaging applications. This is achieved thanks to the photon counting and time-gating capabilities implemented in the analog domain, which in turn enable a 15 μm pixel with a 21% fill-factor. A reconfigurable column circuitry supports both the analog conventional readout and a self-referenced analog-to-digital conversion, able to cancel out the pixel-to-pixel nonuniformities, and speeding up the framerate to 486 fps. The imager, featuring also a delay locked loop to stabilize the internal waveform generation for reliable timing performance, has been implemented in a standard high-voltage 0.35 μm CMOS technology. Measurements in a fluorescent lifetime setup have been performed, comparing the results with single-point acquisitions made with commercial time-correlated equipment.

We present a Montecarlo simulator developed in Matlab^® for the analysis of a Single Photon Avalanche Diode (SPAD)-based Complementary Metal-Oxide Semiconductor (CMOS) flash Light Detection and Ranging (LIDAR) system. The simulation environment has been developed to accurately model the components of a flash LIDAR system, such as illumination source, optics, and the architecture of the designated SPAD-based CMOS image sensor. Together with the modeling of the background noise and target topology, all of the fundamental factors that are involved in a typical LIDAR acquisition system have been included in order to predict the achievable system performance and verified with an existing sensor.

This article reports the design and characterization of a 32 x 32 single-photon avalanche diode (SPAD) time-resolved image sensor for quantum imaging applications fabricated in a 150-nm CMOS standard technology. A per-SPAD time-to-digital converter (TDC) records the spatial cross correlation functions of a flux of entangled photons. Each 44.64-μm pixel with 19.48% fill-factor features a 210.2-ps resolution, 50-ns (8-bit) range TDC with 1.28-LSB differential and 1.92-LSB integral nonlinearity (DNL/INL). The sensor achieves an observation rate of up to 1 MHz through a current-based mechanism that avoids reading empty frames when the photon rates are low. A row-skipping mechanism detects the absence of SPAD activity in a row to increase the duty cycle. These two features require only three transistors in each pixel. The sensor functionality is demonstrated in a quantum imaging experiment that achieves super-resolution.

We present an FPGA implementation of a Timeto- Digital Converter based on a low cost, low area Spartan 6 device. The converter is based on a tapped delay line model. Several implementation details are discussed with particular focus on critical blocks such as the input stage and thermometerto- binary decoding techniques. We implemented a tap filtering technique to improve the differential non-linearity (DNL) of the single delay line while keeping a good LSB value of 25.57 ps with a single-shot precision (SSP) between 0:69 ÷ 1:46 LSB. Measured DNL and INL lie in the range between −0:90 ÷ 1:23 and −0:43 ÷ 2:96 LSB, respectively. We then implemented an interpolating TDC to overcome the limitations of a single delay line in terms of linearity and measurement range. The interpolating TDC uses the sliding scale technique, where the time interval to be measured is asynchronous with respect to the FPGA clock, achieving DNL and INL in the range −0:072 ÷ 0:070 and −0:755 ÷ 0:872 LSB. SSP is in the 1:096 ÷ 2:815 range. Moreover, we present a novel comparison between the DNLs obtained with two different methods: statistical code density test and using a finely-controlled delay source. Finally, we present the results of a Montecarlo simulation used to investigate the effects of non-linear propagation of the signal through the delay line.