A high voltage, external capacitor-less low-dropout regulator (HVLDO) with transient enhancement loop is presented in this work. The proposed HVLDO is designed with high withstand voltage laterally-diffused MOS (LDMOS) transistors and a transient enhancement loop is proposed to properly inject/sink current to/from the gate and output nodes of the power transistors to achieve fast transient response and high stability. Fabricated in 0.5 μm SOI BCD process, the HVLDO occupies an active area of 0.29 mm2. Operating with an input voltage ranging from 5.2 to 20 V, it supplies an output voltage of 5 V and a maximum load of 100 mA. For all load conditions, this design has the power supply rejection of -49 dB@ 100 kHz, the phase margin over 68.4 deg and achieves a temperature coefficient of 13.15 ppm/°C. Measurement results show that this design has a line regulation of 0.88 mV/V and a load regulation of 0.22 mV/mA. The proposed HVLDO features fast line transient response of 60/20 mV@ 9.8 V/µs, fast load transient response of 30/70 mV@100 mA/µs, and recovery time of 2 µs without external capacitors. Compared with the prior art, this work achieves the best transient FOM of 12.19 fs.

Radiation effects of a 150 keV proton beam with various fluences on GaN-based quasi-vertical p–i–n diodes are investigated. For fundamental analysis, the electrical properties of P-GaN and N⁻-GaN separated from p–i–n diodes are also investigated. With the increase in the radiation-induced defect (e.g., V_N and V_Ga) density, the carrier concentrations and mobilities of P-GaN and N⁻-GaN decrease significantly. Under the proton fluence of 1 × 10¹⁵ p/cm², P-GaN has been transformed into highly resistive N-GaN, resulting in p–i–n diodes losing electrical characteristics of the PN junction. Meanwhile, the P-GaN Ohmic contact has been converted to Schottky contact. In addition, due to a large number of radiation-induced defects in P-GaN and N⁻-GaN, the reverse leakage current mechanism is revealed to change from space-charge-limited current conduction to Ohmic conduction.

Based on an 0.18 μm process, this paper proposes a fully integrated 1.8 V output 300 mA load low-dropout linear regulator (LDO) with a fast transient response. By inserting a transient-enhanced biased Class AB super source follower at the gate of the output power transistor, this LDO can quickly adjust the gate voltage of the power transistor without additional power consumption. By adding an active capacitor circuit composed of a fast comparator with offset voltage at the output point, this LDO can quickly charge/discharge the transient current and accelerate the transient response without reducing the circuit stability. Simulation results show that the proposed LDO has an output voltage of 1.8 V, when the input voltage is 2 V to 5 V while consuming 66.4 μA of quiescent current. The proposed capless LDO has a 1.94 µV/mA load regulation, a 0.55 mV/V linear regulation, and a −60 dB@1 kHz power supply rejection. When the load current steps from 3 mA to 300 mA in 300 ns, the LDO settles in 400 ns with an overshoot and undershoot of 67 mV and 86 mV, respectively.

A novel capacitor-less low-dropout regulator (CL-LDO) is presented that achieves transient and stability enhancements through the addition of an active capacitor and a dynamically biased buffer. To enhance the transient response, an active capacitor is proposed, resulting in a significant reduction in overshoot, undershoot, and settling time. Furthermore, the dynamically-biased buffer, comprised of a super-gm source follower, effectively enhances the loop stability. Implemented and fabricated in 0.18 μm SOI BCD technology, the CL-LDO generates a stable output voltage of 1.8 V in the input voltage range from 2.8 V to 3.8 V, with a maximum load current of 100 mA and a quiescent current of 94 µA. When the load current steps from 0 mA to 100 mA, the measured results of overshoot and undershoot are 240 mV and 110 mV, respectively. The proposed CL-LDO has superior line regulation of 0.94 mV/V and load regulation of 12.66 mV/A.

In this work, the electrostatic discharge (ESD) characteristics of a pMOS-triggered bidirectional silicon-controlled rectifier (PTBSCR) that was fabricated in a 0.18 μm silicon-on-insulator (SOI) bipolar-CMOS-DMOS (BCD) process, is investigated. The multi-snapback phenomenon was observed under the transmission line pulsing (TLP) test system. It was found that gate voltage and inserting shallow trench isolation (STI) can significantly affect the trigger voltage and holding voltage. The underlying physical mechanism related to the multi-snapback phenomenon and the effects of gate voltage on the critical parameters was investigated through the experimental results and the assistance of technology computer-aided design (TCAD) simulations. The adjustments of gate voltage and STI on the critical ESD parameters of the device provide an effective design idea for low-voltage ESD protection in the SOI BCD process.