The TID effect of low operation voltage MOSFET (LV-MOS), medium operation voltage lateral double-diffused MOSFET (MV-LDMOS), and 600V high operation voltage LDMOS (HV-LDMOS) manufactured by SOI BCD process is investigated by experiments and 3D TCAD numerical simulations and the hardening technique is proposed and discussed. The experiment and simulation results of LV-MOS with three different structures indicate that the TID-induced leakage current is mainly caused by the STI oxide, which forms a leakage current path along the side of channel region. The leakage current of LV-MOS with a square/ring shape gate structure does not increase even though the irradiation dose increases to 300 krad(Si). The square/ring shape gate structure can eliminate the TID-induced leakage current induced by segregating the channel from STI region, which is used in MV-LDMOS and 600V HV-LDMOS. The TID-induced leakage current of radiation-hardened MV-LDMOS does not increase at the irradiation dose of 300 krad(Si). The TID-induced leakage current of radiation-hardened 600V HV-LDMOS is about four orders of magnitude less than that of standard 600V HV-LDMOS at the irradiation dose of 50 krad(Si). The specific-on-resistance performance of MV-LDMOS and 600V HV-LDMOS is improved with the increase of irradiation dose. The radiation-hardened technique used in this paper can improve the TID tolerance of MOSFETs in SOI BCD process significantly. The systematic and thorough investigation of TID hardening technique of SOI BCD technology will contribute to the application of power ICs in space environment.

In this article, high-voltage (HV) electrostatic discharge (ESD) protection devices with high robustness and strong radiation tolerance are investigated by technology computer-aided design (TCAD) simulations and transmission line pulse (TLP) measurements. The TLP measurement results of laterally diffused MOS (LDMOS)-silicon-controlled rectifier (SCR) fabricated in $0.35 \mu \text{m}$ bipolar-CMOS-DMOS (BCD) process demonstrated that its ESD robustness is elevated by 58% than that of LDMOS and is up to 13 kV human body model protection level. Meanwhile, high holding voltage and current of 17 V and 1.8 A are achieved by low-voltage MOS (LV-MOS) cascade technology in LDMOS-SCR. TLP ${I}$ – ${V}$ curves and transient voltage waveforms exhibit high operational stability of LDMOS-SCR. Gamma-ray irradiation experiments show strong radiation tolerance of LDMOS-SCR, whose ESD performance had almost no degradation under total ionizing dose (TID) radiation of 200 krad(Si), while the failure current of LDMOS decreased by 2 A. Therefore, a properly designed LDMOS-SCR is an excellent ESD protection device for HV circuits, especially in space applications.

The total ionizing dose (TID) effect in p-type top-gate CNT FET under ON, OFF, TG, and All-0 bias conditions is investigated through experiments and simulations. The continuous application of electrical stress incites degradation in the device characteristics of CNT FETs, which is further complicated by the superimposition of TID effects. This work distinguished between the electrical stress impact and the TID effect through comparative experiments and analyzed the underlying mechanisms of these two effects with TCAD simulations. The experimental results demonstrate that both effects on CNT FETs mainly result in a threshold voltage shift. Electrical stress results in a ΔV_th of -0.1 V (OFF state) to +0.2 V (ON state), while TID effect results in a ΔV_th of -0.15 V (TG state) to -0.05 V (ON and OFF state). The TG state is recognized as the worst-case bias condition of TID effect on CNT FETs. TCAD simulation results denote that electrical stress incites changes in the trap charge density (~10¹² cm^-2) within the gate dielectric layer, while the TID effect augments positive fixed charges (~10¹¹ to 10¹² cm^-2) in the substrate oxide. This study explains the mechanisms of electrical stress and TID effects in CNT FETs, providing a reference for subsequent device process optimization and radiation hardening.

A novel implementation for electrostatic discharge (ESD) protection is demonstrated, which involves two structures named MOSFET in parallel with diode (MOS-DIO) and MOSFET in parallel with silicon-controlled rectifier (MOS-SCR). The fabricated structures exhibit enhanced robustness enabled through the double silicon-on-insulator (DSOI) technology. The implementation combines a MOSFET in the top silicon film with a diode or a silicon-controlled rectifier (SCR) located in the middle silicon layer. Transmission line pulse (TLP) experiments show that compared with the traditional single nMOS structure, both DSOI MOS-DIO and MOS-SCR exhibit superior current discharge capability with an increase in failure current of up to 39% under the same footprint. The leakage of the proposed structures is also reduced to below 0.2 pA/ $\mu \text{m}$ thanks to the double buried oxide isolation. In addition, both triggering and holding voltages can be flexibly tuned via the positioning of the two shunt devices. Technology computer-aided design (TCAD) simulations were carried out for MOS-SCR to interpret the physical mechanism and predict the performance under different device parameters, including gate length, stacked modes, and ambient temperature.

The ongoing trend towards miniaturization and increased packaging density has exacerbated the reliability problem of Au-Al heterogeneous metal bonding structures in high-temperature environments, where extreme temperatures and high current pose a serious challenge. In order to address this issue, the present study aims to investigate the electromigration reliability of Au-Al bonding by comparing the conventional heterogeneous contacts with OPM structures, which are homogeneous contacts. A novel bonding layout was developed to precisely detect the resistance and obtain stage changes in electromigration. The experimental results demonstrated that the relative resistance shift of Au-Al bonding at 250 °C was 98.7%, while CrAu and NiPdAu OPM structures exhibited only 46.1% and 2.93% shifts, which suggests that the reliability of OPM structures was improved by a factor of 2.14 and 33.6, respectively. The degradation of Au-Al bonding was attributed to the large cracks observed at the bonding interface and lateral consumption of Al elements. In contrast, OPM structures only exhibited tiny voids and maintained a better bonding state overall, indicating that homogeneous metal contacts have better immunity to electromigration. Furthermore, this study also observed the polarity effect of electromigration and analyzed the impact of NiPdAu thickness on reliability. Overall, this research provides a novel approach and an insightful theoretical reference for addressing the bottleneck of high-temperature electromigration reliability in high-temperature sensor packaging.