Gate-all-around (GAA) field-effect transistors have been proposed as one of the most important developments for CMOS logic devices at the 3 nm technology node and beyond. Isotropic etching of silicon–germanium (SiGe) for the definition of nano-scale channels in vertical GAA CMOS and tunneling FETs has attracted more and more attention. In this work, the effect of doping on the digital etching of Si-selective SiGe with alternative nitric acids (HNO₃) and buffered oxide etching (BOE) was investigated in detail. It was found that the HNO₃ digital etching of SiGe was selective to n⁺-Si, p⁺-Si, and intrinsic Si. Extensive studies were performed. It turned out that the selectivity of SiGe/Si was dependent on the doped types of silicon and the HNO₃ concentration. As a result, at 31.5% HNO₃ concentration, the relative etched amount per cycle (REPC) and the etching selectivity of Si_0.72Ge_0.28 for n⁺-Si was identical to that for p⁺-Si. This is particularly important for applications of vertical GAA CMOS and tunneling FETs, which have to expose both the n⁺ and p⁺ sources/drains at the same time. In addition, the values of the REPC and selectivity were obtained. A controllable etching rate and atomically smooth surface could be achieved, which enhanced carrier mobility.

The ongoing trend towards miniaturization and increased packaging density has exacerbated the reliability problem of Au-Al heterogeneous metal bonding structures in high-temperature environments, where extreme temperatures and high current pose a serious challenge. In order to address this issue, the present study aims to investigate the electromigration reliability of Au-Al bonding by comparing the conventional heterogeneous contacts with OPM structures, which are homogeneous contacts. A novel bonding layout was developed to precisely detect the resistance and obtain stage changes in electromigration. The experimental results demonstrated that the relative resistance shift of Au-Al bonding at 250 °C was 98.7%, while CrAu and NiPdAu OPM structures exhibited only 46.1% and 2.93% shifts, which suggests that the reliability of OPM structures was improved by a factor of 2.14 and 33.6, respectively. The degradation of Au-Al bonding was attributed to the large cracks observed at the bonding interface and lateral consumption of Al elements. In contrast, OPM structures only exhibited tiny voids and maintained a better bonding state overall, indicating that homogeneous metal contacts have better immunity to electromigration. Furthermore, this study also observed the polarity effect of electromigration and analyzed the impact of NiPdAu thickness on reliability. Overall, this research provides a novel approach and an insightful theoretical reference for addressing the bottleneck of high-temperature electromigration reliability in high-temperature sensor packaging.

In this work, the electrostatic discharge (ESD) characteristics of a pMOS-triggered bidirectional silicon-controlled rectifier (PTBSCR) that was fabricated in a 0.18 μm silicon-on-insulator (SOI) bipolar-CMOS-DMOS (BCD) process, is investigated. The multi-snapback phenomenon was observed under the transmission line pulsing (TLP) test system. It was found that gate voltage and inserting shallow trench isolation (STI) can significantly affect the trigger voltage and holding voltage. The underlying physical mechanism related to the multi-snapback phenomenon and the effects of gate voltage on the critical parameters was investigated through the experimental results and the assistance of technology computer-aided design (TCAD) simulations. The adjustments of gate voltage and STI on the critical ESD parameters of the device provide an effective design idea for low-voltage ESD protection in the SOI BCD process.

The self-heating effect (SHE) of silicon-on-insulator (SOI) MOSFETs brings challenges to the measurement and modeling of transient electrothermal characteristics. For the first time, this study obtains the transient two-stage thermal equivalent RC network of SOI MOSFETs by nano double-pulse measurement combined with network identification by a deconvolution (NID) method. The two-stage model provides a comprehensive reference for the accumulation of residual heat under dynamic operation. We reveal that since the oxide layer acts as a thermal reservoir, the heat dissipation process can be divided into three phases according to thermal time constants. The results of geometry dependence of thermal parameters show that the gate length and width-to-length ratio ( ${W}/{L}$ ) increase: the thermal resistance trend of both stages decreases, the one-stage thermal time constant increases, but the two-stage thermal time constant decreases. Also, as the scaling of device dimension and mutual thermal coupling, the thermal transient response boosts significantly.