Hafnium-based Ferroelectric Field-Effect Transistors (FeFETs) suffer from limited endurance. In-depth understanding of the trap behaviour during failure process is crucial for endurance improvement. In this work, aiming at the characteristics of FeFETs, Trap Spectroscopy by Charge Injection and Sensing (TSCIS) technique is optimized and an advanced trap characterization platform based on newly optimized TSCIS method combined with Low Frequency Noise (LFN) and C-V characteristics for resolving spatial and energetic distribution of traps in FeFETs is developed. Furthermore, through this advanced trap characterization platform, the trap behaviours of nitridation/non-nitridation FeFETs during endurance process are characterized and compared in detail. The improvement of interface quality by nitridation is finally confirmed from the defect level.

We study the impact of different interlayers (ILs) and ferroelectric materials on charge trapping during the endurance fatigue of Si ferroelectric field effect transistor (FeFET) with TiN/Hf _x Zr _1-x O ₂ / interlayer/Si (MFIS) gate-stack. We have fabricated FeFET devices with different interlayers (SiO ₂ or SiON) and Hf _x Zr _1-x O ₂ materials ( ${x} =0.75$ , 0.6, 0.5) and directly extracted the charge trapping during endurance fatigue. We find that: 1) under the same equivalent oxide thickness (EOT) condition, the increase of dielectric constant and interlayer thickness suppresses charge trapping and improves the endurance characteristics; 2) charge trapping effect is experimentally verified to be the origin of endurance fatigue; and 3) as the spontaneous polarization ( ${P}_{\text {s}}{)}$ of the Hf _x Zr _1-x O ₂ decreases from $25.9~ \boldsymbol {\mu } \text{C}$ /cm ² (Hf _0.5 Zr _0.5 O ₂ ) to $20.3~ \boldsymbol {\mu } \text{C}$ /cm ² (Hf _0.6 Zr _0.4 O ₂ ), the charge trapping behavior decreases, resulting in the slow degradation rate of memory window (MW) during program/erase cycling; in addition, when ${P}_{\text {s}}$ further decreases to $8.1~ \boldsymbol {\mu }\text{C}$ /cm ² (Hf _0.75 Zr _0.25 O ₂ ), the initial MW nearly disappears (only ~0.02 V). Thus, the reduction of ${P}_{\text {s}}$ could improve endurance characteristics. On the contrary, it can also reduce the MW. Our work helps design the MFIS gate-stack to improve endurance characteristics.

We investigate the charge trapping during endurance fatigue of FeFET with TiN/Hf _0.5 Zr _0.5 O ₂ /SiO ₂ /Si (MFIS) gate structure. We propose a method of experimentally extracting the number of trapped charges during the memory operation, by measuring the charges in the metal gate and Si substrate. We verify that the amount of trapped charges increases during the endurance fatigue process. This is the first time that the trapped charges are directly experimentally extracted and verified to increase during endurance fatigue. Moreover, we model the interplay between the trapped charges and ferroelectric polarization switching during endurance fatigue. Through the consistency of experimental results and simulated data, we demonstrate that as the memory window (MW) decreases: 1) the ferroelectric characteristic of Hf _0.5 Zr _0.5 O ₂ is not degraded; 2) the trap density in the upper bandgap of the gate stacks increases; and 3) the reason for MW decrease is increased trapped electrons after program operation but not related to hole trapping/detrapping. Our work is helpful to study the charge trapping behavior of FeFET and the related endurance fatigue process.

In this work, we demonstrate the enlargement of the memory window of Si channel FeFET with ferroelectric Hf _0.5 Zr _0.5 O ₂ by gate-side dielectric interlayer engineering. By inserting a 3 nm Al ₂ O ₃ dielectric interlayer between TiN gate metal and ferroelectric Hf _0.5 Zr _0.5 O ₂ , we achieve a memory window of 4.1 V with endurance of ~10 ⁴ cycles and retention over 10 years. The physical origin of memory window enlargement is clarified to be charge trapping at the Al ₂ O ₃ /Hf _0.5 Zr _0.5 O ₂ interface, which has an opposite charge polarity to the trapped charges at the Hf _0.5 Zr _0.5 O ₂ /SiO _x interface.

The nitridation process can significantly improve the quality of the interfacial layer and suppress the unrecoverable electron trapping of the interfacial states during cycling, which is the main cause of endurance enhancement. In this work, through in-depth analysis of defect behavior during memory window (MW) degradation in ferroelectric field effect transistors (FeFETs), it is found that the degradation of FeFET devices with SiON interfacial layer starts within the HZO layer, while the degradation process of FeFET devices with SiO2 interlayer initially begins at the interlayer and then penetrates into the HZO layer. First, the MW degradation processes of nitridation/non-nitridation devices are measured and compared. Moreover, through the extended measure-stress-measure method, three types of defects are defined and the defect behaviors including trapping kinetics and energy locations during degradation are systematically investigated. The mechanism of nitrogen on the endurance enhancement is finally revealed. These results are valuable to better understand the reliability issues of FeFET and pave the way for future process optimization.

Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect; a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH₂F₂/CH₄/O₂/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO₂. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node.