Developing E-mode p-channel field-effect transistors (p-FETs) on the standard p-GaN gate HEMT epi-wafer is highly motivated to facilitate the realization of gallium nitride (GaN) complementary logic (CL) circuits and power-integrated circuits (PICs). The gate etching process is commonly employed in the fabrication of E-mode GaN p-FETs. However, due to gate etching-induced damage, the performance of E-mode GaN p-FETs often fails to meet expectations. To address the above issue, a post-etch wet treatment technique was developed in this work to enhance the performance of E-mode GaN p-FETs. The fabricated GaN p-FET with $\textit{L}_{\text{G}}$ $=$ 2 $\mu$ m exhibits an E-mode operation with $\textit{V}_{\text{th}}$ $=$ $-$ 2.9 V. The p-FET with post-etch wet treatment exhibits a current density of 5.4 mA/mm. Compared to the p-FET without wet treatment (1.9 mA/mm), the current density has increased by more than double. Atomic force microscopy (AFM) was utilized to characterize the surface morphology and validate the effectiveness of post-etch wet treatment. To suppress the leakage current, multienergy fluorine ion implantation was implemented for planar isolation of GaN p-FETs, high $\textit{I}_{\text{ON}}$ / $\textit{I}_{\text{OFF}}$ with over 6 $\times$ 10 $^{\text{5}}$ was obtained.

An enhancement-mode (E-mode) p-type gallium nitride (p-GaN) gate high electron mobility transistor with a gate termination extension (GTE-HEMT) has been developed on a sapphire substrate, intended for power switching applications of kilovoltage (kV) level. The GTE-HEMT device exhibits a low ON-resistance ( R $_{\biosc{on}}$ ) of 19.3 $\Omega$ $\cdot$ mm, corresponding to a specific R $_{\biosc{on}}$ ( R $_{\biosc{on},\text{SP}}$ ) of 7.33 m $\Omega$ $\cdot$ cm $^{\text{2}}$ . Notably, the GTE-HEMT has achieved a breakthrough by increasing the breakdown voltage (BV) to 2573 V, surpassing the conventional p-GaN gate HEMT (Conv-HEMT) with its BV of 1679 V. The enhanced BV is ascribed to the gate termination extension (GTE) that reduces the gate-edge electric field peak, similar to a junction termination extension (JTE) in traditional Si power devices. In addition, the dynamic R $_{\biosc{on}}$ of the GTE-HEMT has been improved, with a normalized dynamic R $_{\biosc{on}}$ (dynamic R $_{\biosc{on}}$ /static R $_{\biosc{on}}$ ) of 1.4 and 2.6 for 650-and 1200-V OFF-state stress, respectively. The GTE-HEMT has been benchmarked to the state-of-the-art GaN power transistors, demonstrating its potential for high-voltage applications.

A 650-V p-GaN gate HEMT with Schottky source extension is proposed towards enhanced short-circuit (SC) reliability. At higher drain bias, a pinch-off point is formed at the edge of the Schottky source extension, resulting in reduced saturation current. High-voltage pulse I-V characterization is conducted for the devices in the ON-state to evaluate their SC reliability. With the similar OFF-state breakdown voltages ( BV s), the proposed device survives a much higher SC pulse voltage compared to the conventional p-GaN gate HEMT. Then, multiple short-circuit (SC) stress/test cycles are applied to the devices. For each stress, the drain voltage is increased by 50 V. The progressive degradation of R _ON and OFF-state leakage current are recorded after each SC stress. The degradation of the proposed device is much slower than the conventional device. These results indicate that the proposed device is a promising solution for short-circuit rugged GaN power transistors.

This letter demonstrates a 1200-V E-mode GaN-on-sapphire power transistor based on active passivation technique. The active passivation concept utilizes a thin p-GaN layer extending from the p-GaN gate towards near the drain to screen the surface traps. The fabricated active-passivation HEMT (AP-HEMT) with L _GD of 27 μm exhibits a low R _ON of 16.9 Ω∙mm, corresponding to a specific R _ON ( R _ON,SP ) of 6.42 mΩ·cm ² . A breakdown voltage ( BV ) over 2000 V is obtained for the AP-HEMT. Besides, the AP-HEMT showcased excellent dynamic performance due to the surface shielding effect provided by the active passivation. Dynamic ON-resistance was characterized 120 μs after a 10-ms V _DS -OFF stress. At V _DS-OFF = 1200 V, the ratio of dynamic R _ON to static R _ON is 1.09. The results highlight the superior capabilities of active passivation technique for 1200-V GaN power transistors.

This work investigates the charge balance design of the 1200-V E-mode lateral superjunction p-GaN gate HEMT (SJ-HEMT) on sapphire substrate. The charge balance is formed through the alternative p-/n-pillars; the p-pillars are thinned p-GaN stripes, and the n-pillars are 2DEG stripes. The charge balance design on the static and dynamic performance of the SJ-HEMT was investigated by tuning the width of p-/n-pillars. The SJ-HEMT with charge balance yields a BV of 2655 V and a high BV/ ${L}_{\text {GD}}$ ratio of 1.56 MV/cm. Notably, the SJ-HEMT demonstrates effective suppression of trapping effects, which exhibits a strong correlation with the gap between two p-pillars. At charge balance design, the SJ-HEMT presents an excellent dynamic ${R}_{\text {ON}}$ /static ${R}_{\text {ON}}$ ratio of 1.28 under ${V}_{\text {DS}}$ stress up to 1200 V. Our study also indicates a scaling of p-/n-pillars can further improve the dynamic ${R}_{\text {ON}}$ performance. This work underscores the merits of charge-balanced design for high-performance 1200-V E-mode GaN power transistors.

The low current density in E-mode GaN p-FET presents a severe challenge for its application in complementary logic (CL) circuits. In this work, a high-current E-mode InGaN/GaN p-FET is demonstrated on a p-GaN gate HEMT platform with p-InGaN/p-GaN/AlGaN/GaN heterostructure. The proposed heterostructure introduces a net polarization charge at the InGaN/GaN interface, leading to an enhanced 2DHG. With a negative gate bias, a buried 2DHG channel is formed prior to the surface MIS channel. As a result, the recess-gate InGaN/GaN p-FET with ${L}_{\text {G}} = 2~\mu $ m achieves a large maximum current ( ${I}_{\max }\text {)}$ exceeding −20 mA/mm. The InGaN/GaN p-FET obtains a low ${R}_{\text {ON}}$ of 0.64 k $\Omega \cdot $ mm and a high ${I}_{\text {ON}}$ / ${I}_{\text {OFF}}$ ratio exceeding $10^{{7}}$ . The device presents E-mode operation with a threshold voltage ( ${V}_{\text {TH}}\text {)}$ of −1.8 V and a low subthreshold swing (SS) of 144 mV/dec. Furthermore, an E-mode n-channel GaN HEMT is fabricated on the same platform, validating the potential of the proposed InGaN/GaN p-FET for GaN CL circuits.