High-k dielectric stacks are regarded as a promising information storage media in the Charge Trapping Non-Volatile Memories, which are the most viable alternative to the standard floating gate memory technology. The implementation of high-k materials in real devices requires (among the other investigations) estimation of their radiation hardness. Here we report the effect of gamma radiation (⁶⁰Co source, doses of 10 and 10 kGy) on dielectric properties, memory windows, leakage currents and retention characteristics of nanolaminated HfO₂/Al₂O₃ stacks obtained by atomic layer deposition and its relationship with post-deposition annealing in oxygen and nitrogen ambient. The results reveal that depending on the dose, either increase or reduction of all kinds of electrically active defects (i.e., initial oxide charge, fast and slow interface states) can be observed. Radiation generates oxide charges with a different sign in O₂ and N₂ annealed stacks. The results clearly demonstrate a substantial increase in memory windows of the as-grown and oxygen treated stacks resulting from enhancement of the electron trapping. The leakage currents and the retention times of O₂ annealed stacks are not deteriorated by irradiation, hence these stacks have high radiation tolerance.

The annealing of radiation-induced defects in burn-in stressed n-channel power VDMOSFETs with thick gate oxides (100 and 120 nm) is analysed. In comparison with the previous spontaneous recovery, the changes of device electrical parameters observed during annealing are highlighted by the elevated temperature and voltage applied to the gate, and are more pronounced in devices with a 120 nm thick gate oxide. The threshold voltage of VDMOSFETs with a 100 nm thick gate oxide during annealing has an initially slow growth, but then increases rapidly and reaches the value higher than the pre-irradiation one (rebound effect). In the case of devices with a 120 nm thick gate oxide, the threshold voltage behaviour also consists of a slight initial increase followed by a rapid, but dilatory increase, with an obvious tendency to achieve the rebound. The changes of channel carrier mobility during annealing are similar in all samples: at first, it slowly and then rapidly declines, and after reaching the minimum it begins to increase. In the case of VDMOSFETs with a thicker gate oxide, these changes are much slower. The underlying changes in the densities of gate oxide-trapped charge and interface traps are also delayed in devices with a thicker gate oxide. All these phenomena occur with certain delay in burn-in stressed devices compared to unstressed ones. The leading role in the mechanisms responsible for the observed phenomena is attributed to hydrogen related species.

This study examines the effects of negative bias temperature (NBT) stress on irradiated commercial p-channel power VDMOS transistors, with a focus on contribution to threshold voltage shift of changes in gate oxide charge and interface traps. The research addresses the critical reliability concerns for these transistors, as shifts in the threshold voltage can notably influence device performance, particularly under conditions of elevated temperature and negative gate oxide fields. Considering that VDMOS transistors are power devices, high temperatures occur during their operation, which can cause NBT effects, and this definitely affects normal operation. Furthermore, the study investigates the implications of irradiation on the electrical parameters of VDMOS power transistors, highlighting the need for a thorough understanding of these effects. The experimental methodology includes both irradiation and subsequent NBT stress application. This paper provides a detailed analysis of both static and pulsed NBT stressing, with an emphasis on novel stress signals related to practical applications. The data presented in the paper were obtained by exposing components to NBT stresses with different polarizations on the gate, which were previously exposed to radiation to different doses, with and without polarization. Also, the results with different frequencies applied during NBT stress are presented. Results from the study elucidate the roles of gate oxide charge and interface traps in contributing to threshold voltage shifts, thereby offering critical insights into the reliability of p-channel power VDMOS transistors in various operational stress scenarios. Self-heating during both the operational and cooling phases of fresh and previously irradiated components were measured using IR camera These findings are instrumental for the design and operation of electronic systems that utilize these transistors, ensuring improved reliability and performance.

This study investigates the reliability and performance of p-channel power VDMOS transistors subjected to different stresses NBT, PBT, HEF, and irradiation. Results reveal distinct degradation patterns in electrical parameters, with threshold voltage shifts particularly affected. Notably, positive HEF stress can produce a „turn-around“ effect in investigated devices. Also, irradiated devices show degradation trends similar to those under HEF stress, emphasizing the influence of ionizing radiation on stability. Additionally, self-heating effects in stressed devices highlight vulnerability under real operating conditions. These findings are crucial for enhancing the reliability of VDMOS transistors in high-stakes applications such as automotive, aerospace, and high-reliability switching circuits.

In this paper, the impact of negative bias temperature instabilities (NBTIs) on commercial power p-channel Vertical Double-Diffused MOS (VDMOS) transistors from the standpoint of practical applications was analyzed. The effects of NBTI are one of the main reliability concerns for this type of device, so it is necessary to investigate how these effects influence various applications. A series of experiments were carried out including negative bias temperature stressing, infra-red thermographic recording and circuit characterization, with the goal of evaluating the effects of negative bias temperature stressing on the self-heating of samples in load-driving circuits operating with higher currents and circuit performance of a CMOS inverter circuit containing the examined samples. The findings suggest that negative bias temperature stressing-induced threshold voltage shift directly affects increased self-heating in load-driving circuits and that it also directly affects transfer and dynamics characteristics in CMOS inverters.

This study investigates the effects of negative bias temperature (NBT) stress and irradiation on the threshold voltage (V_T) of p-channel VDMOS transistors, focusing on degradation, recovery after each type of stress, and operational behavior under varying conditions. Shifts in V_T (ΔV_T) were analyzed under different stress orders, showing distinct influence mechanisms, including defects creation and their removal and electrochemical reactions. Recovery data after each type of stress indicated ongoing electrochemical processes, influencing subsequent stress responses. Although the ΔV_T is not particularly pronounced during the recovery after irradiation, changes in subthreshold characteristics indicate the changes in defect densities that affect the behavior of the components during further application. Additionally, the findings show that the ΔV_T during the NBT stress after irradiation (up to certain doses and conditions) remains relatively stable, but this is the result of a balance of competing mechanisms. A subthreshold characteristic analysis provided a further insight into the degradation dynamics. A particular attention was paid to analyzing ΔV_T with a focus on predicting the lifetime. In practical applications, especially under pulsed operation, prior stresses altered the device’s thermal and electrical performance. It was shown that self-heating effects were more pronounced in pre-stressed components, increasing the power dissipation and thermal instability. These insights additionally highlight the importance of understanding stress-induced degradation and recovery mechanisms for optimizing VDMOS transistor reliability in advanced electronic systems.