This paper presents a digitally programmable bi-directional 7-bit passive phase shifter in a 65 nm CMOS technology. The core of this passive vector-synthesized phase shifter is a hybrid quadrature generator (HQG), an interstage matching network, and a passive vector modulator (PVM). This work proposes a high coupling-factor-based quadrature generator design methodology and demonstrates it with a compact vertical transformer. The interstage matching network between HQG and PVM is proposed to release the bandwidth bottleneck and achieve a 34% fractional frequency bandwidth. Two 6-bit X-type attenuators in the I and Q path form a high-resolution 12-bit controlling word. In 32–40 GHz, this 7-bit 360° phase shifter achieves a measured 2.8° step with 0.45-1.6° RMS phase error and 0.2-0.36 dB RMS magnitude error. With the broadband technique, its 3-dB bandwidth reaches 30.2-42.7 GHz with a 2.8° RMS phase error. Its in-band 1-dB compression point is 10.2 dBm. With the proposed compact HQG and PVM, this mm-wave passive phase shifter only occupies $220\times 630\,\,\mu \text{m}^{2}$ and has no power consumption.

This article presents a 76–81 GHz millimeter-wave (mm-wave) radar transceiver and a 2 $\times$ 8 multi-input multi-output (MIMO) antenna-in-package (AiP) for automotive radar applications. The proposed transceiver chip consists of a frequency-modulated-continuous-wave (FMCW) radar waveform generator, a 3-channel sub-transmitter (Tx), and a 4-channel receiver (Rx) with integrated analog-to-digital converters (ADC). A two-point modulation scheme and a digital-to-analog converter’s (DAC) dynamic bias technique are adopted in the FMCW generator to achieve fast chirps and broad modulation bandwidth. A maximum modulation bandwidth of 7.2 GHz is measured. A measured maximum chirp rate reaches 312 MHz/ $\mu$ s while the rms linearity stays less than 0.32%. The measured best-case chirp linearity peak error is 0.018% when the chirp rate is set as 9.21 MHz/ $\mu$ s. Two transceiver chips operating in a primary-secondary mode, 2 Tx antennas, and 8 Rx antennas are packaged in the embedded glass fan-out (eGFO) technology for better detection capability. Each Tx patch antenna is fed by three power amplifier (PA) outputs through a coaxial feeding structure. The measured Tx effective isotropic radiated power (EIRP) is improved by 7.5 dB compared to a single-feed antenna. Therefore, the chipset demo shows a detection range of up to 38.5 m. The transceiver chip is fabricated in a 65 nm CMOS technology and occupies 5.8 $\times$ 5.8 mm $^2$ . The packaged 2 $\times$ 8 MIMO AiP chipset is 24 $\times$ 24 mm $^2$ .

This paper presents the design and measurement of an interpolation-based low noise and variable gain cell (IBA-cell) in the 60-GHz band, using a 40-nm CMOS technology. The interpolation-based gain cell is designed for an innovative analog beamforming front end, where the array pattern is not only controlled in the phase domain, but also wins the flexibility in the magnitude domain. The circuit specifications are first derived for the application at 60 GHz. Techniques to combine low noise figure (NF) with variable gain tuning are presented focusing on the NF and linearity (IIP₃) on the example of a 60-GHz low noise amplifier and variable gain amplifier. Subsequently, the design and measurement of the whole gain cell (IBA-cell) integrated into a single chip are reported with the technique of a cross-coupled feedback loop to reduce the phase variations over the gain tuning states and enhance the variations of IIP₃. The IBA-cell achieves 15.8-dB maximum gain and 6.5-dB NF at 57 GHz with the gain tuning range from -2 to 15.8 dB and IIP₃ varying from -11.3 to -16 dBm over the gain control range. The IBA-cell consumes a dc power of maximum 54 mA from 1.1 V.

This article presents a broadband sub-terahertz (THz) power amplifier (PA) with a low-loss four-way power combiner. The proposed power combiner consists of an improved zero-degree combiner (ZDC) and a three-conductor Marchand balun simultaneously achieving broadband matching and power combining. The proposed three-conductor Marchand balun adopts a dual- $LC$ tank technique by merging two resonators, and it can be equivalent to a transformer-based multi-resonating network. The power distribution is realized by one input power splitter generating two pairs of differential signals and two parallel 1-to-2 active power splitters. This hybrid distribution driving network further enhances efficiency and power gain. Based on these improvements, a high-output-power sub-THz PA with superior efficiency has been fabricated in the 130-nm SiGe bipolar complementary metal oxide silicon field effect transistor (BiCMOS) technology. The three-stage PA achieves a peak power gain of 16.4 dB, 3-dB small-signal gain bandwidth of 52 GHz from 211 to 263 GHz, a measured maximum saturated output power of 14.7 dBm at 224 GHz, and a peak power-added efficiency (PAE) of 3.13% at 220 GHz. The folded input splitter and extremely compact power combining methodology lead to a core area of 770 $\mu \text{m}\,\,\times \,\,280\,\,\mu \text{m}$ .