GaN high-electron-mobility transistors (HEMTs) are promising next-generation devices in the power electronics field which can coexist with silicon semiconductors, mainly in some radiation-intensive environments, such as power space converters, where high frequencies and voltages are also needed. Its wide band gap (WBG), large breakdown electric field, and thermal stability improve actual silicon performances. However, at the moment, GaN HEMT technology suffers from some reliability issues, one of the more relevant of which is the dynamic on-state resistance (R_{ON_dyn}) regarding power switching converter applications. In this study, we focused on the drain-to-source on-resistance (R_DSON) characteristics under ⁶⁰Co gamma radiation of two different commercial power GaN HEMT structures. Different bias conditions were applied to both structures during irradiation and some static measurements, such as threshold voltage and leakage currents, were performed. Additionally, dynamic resistance was measured to obtain practical information about device trapping under radiation during switching mode, and how trapping in the device is affected by gamma radiation. The experimental results showed a high dependence on the HEMT structure and the bias condition applied during irradiation. Specifically, a free current collapse structure showed great stability until 3.7 Mrad(Si), unlike the other structure tested, which showed high degradation of the parameters measured. The changes were demonstrated to be due to trapping effects generated or enhanced by gamma radiation. These new results obtained about R_{ON_dyn} will help elucidate trap behaviors in switching transistors.

Nowadays, high-performance microprocessors are demanded in many fields, including those with high-reliability requirements. Commercial microprocessors present a good tradeoff between cost, size, and performance, albeit they must be adapted to satisfy the reliability requirements when they are used in harsh environments. This work presents a high-end multiprocessor hardened with macrosynchronized lockstep and additional protections. A commercial dual-core Advanced RISC Machine (ARM) cortex A9 has been used as a case study and a complete hardened system has been developed. Evaluation of the proposed hardened system has been accomplished with exhaustive fault injection campaigns and proton irradiation. The hardening approach has been accomplished for both baremetal applications and operating system (OS)-based. The hardened system has demonstrated high reliability in all performed experiments with error coverage up to 99.3% in the irradiation experiments. Experimental irradiation results demonstrate a cross-sectional reduction of two orders of magnitude.

The effects of ionizing radiation on field-programmable gate arrays (FPGAs) have been investigated in depth during the last decades. The impact of these effects is typically evaluated on implementations which have a deterministic behavior. In this article, two well-known true-random number generators (TRNGs) based on sampling jittery signals have been exposed to a Co-60 radiation source as in the standard tests for space conditions. The effects of the accumulated dose on these TRNGs, an in particular, its repercussion over their randomness quality (e.g., entropy or linear complexity), have been evaluated by using two National Institute of Standards and Technology (NIST) statistical test suites. The obtained results clearly show how the degradation of the statistical properties of these TRNGs increases with the accumulated dose. It is also notable that the deterioration of the TRNG (non-deterministic component) appears before that the degradation of the deterministic elements in the FPGA, which compromises the integrated circuit lifetime.

This work presents the evaluation of a new dual-core lockstep hybrid approach aimed to improve the fault tolerance in microprocessors. Our approach takes advantage of modern multicore processor resources to combine software-based lockstep with a custom hardware observer. The first is used to duplicate data and instruction flows; meanwhile, the second is in charge of the control-flow monitoring. The proposal has been implemented in a dual-core ARM microprocessor and validated with low-energy proton irradiation and emulated fault injection campaigns. The results show an improvement of one order of magnitude in the cross section of the benchmarks tested, even considering the worst case scenario.

Graphic processing units (GPUs) have become a basic accelerator both in high-performance nodes and low-power system-on-chip (SoC). They provide massive data parallelism and very high performance per watt. However, their reliability in harsh environments is an important issue to take into account, especially for safety-critical applications. In this article, we evaluate the influence of the parallelization strategy on the reliability of lower–upper (LU) decomposition on a GPU-accelerated SoC under proton irradiation. Specifically, we compare a memory bound and a compute bound implementation of the decomposition on a K20A GPU embedded on a Tegra K1 (TK1) SoC. We leverage the GPU and CPU clock frequencies both to highlight the radiation sensitivity of the GPU where we are running the benchmark and also to apply both algorithms to solve problems with the same size when exposed to the same radiation dose. Results show that more intensive use of the resources of the GPU increases the cross section. We also observed that most of the radiation-induced errors hang the operating system and even the rebooting process. Finally, we present a preliminary study of the error propagation of the LU decomposition algorithms.