Ultraviolet (UV) photodetectors are key devices required in the industrial, military, space, environmental, and biological fields. The Schottky barrier (SB)-MOSFET, with its high hole and electron barrier, and given its extremely low dark current, has broad development prospects in the optoelectronics field. We analyze the effects of trap states on the output characteristics of an inversion mode n-channel GaN SB-MOSFET using TCAD simulations. At the oxide/GaN interface below the gate, it was demonstrated that shallow donor-like traps were responsible for degrading the subthreshold swing (SS) and off-state current density (I_off), while deep donor-like traps below the Fermi energy level were insignificant. In addition, shallow acceptor-like traps shifted the threshold voltage (V_t) positively and deteriorated the SS and on-state current density (I_on), while deep acceptor-like traps acted on a fixed charge. The output characteristics of the GaN SB-MOSFET were related to the resistive GaN path and the tunneling rate due to the traps at the metal (source, drain)/GaN interface. For the UV responses, the main mechanism for the negative V_t shift and the increases in the I_on and spectral responsivity was related to the photo-gating effect caused by light-generated holes trapped in the shallow trap states. These results will provide insights for UV detection technology and for a high-performance monolithic integration of the GaN SB-MOSFET.

An extended single-sided row hammer (ESH) attack—a novel variant of the row hammer vulnerability—is proposed for the first time in 10 nm-class dynamic random-access memory (DRAM). This method enhances the single-sided row hammer (SH) technique by utilizing a transfer line to induce bit flips in memory cells that are not directly adjacent to the aggressor row. Unlike the double-sided row hammer (DH), which applies repeated pulses to both neighboring word lines of a victim row, the proposed ESH mechanism can induce bit flips with relatively fewer pulses on an adjacent word line, thereby disturbing cells beyond the immediate neighbors. Furthermore, the influence of interface trap density (D_it) at the silicon fin–trench oxide interface is investigated as a key factor affecting the severity of ESH attacks. Simulation results demonstrate that a higher D_it intensifies the lateral electric field and increases electron current density, thereby accelerating charge loss in the memory node. 3D TCAD simulations confirm that these amplified electrical effects exacerbate ESH-induced bit flips. These findings underscore the necessity for novel refresh schemes capable of addressing indirect disturbance mechanisms in DRAM systems.

This study investigates the impact of four parameters—gate angles, fin height controlled through gate overlaps and the distance from fin to source/drain, and substrate bottom doping concentration—on the row hammer effect (RHE) in DRAM cells. The influence of adjacent and passing gates on the DRAM cell body potential was identified as a key factor in D0 and D1 failures. The tolerance for D1 and D0 failures was analyzed, defined as the threshold number of pulses required to induce a 0.6 V change in the storage node voltage (from 1.2 V to 0.6 V for a D1 failure or from 0 V to 0.6 V for a D0 failure). D1 (D0) failure tolerances with the slope from the top of the top gate (θ_angle) of 3°, the height of the TiN gate covering the fin (H_{fin_overlap}) of 12.5 nm, and the height of the fin (H_fin) of 12.5 nm are 1.26 × 10⁶ (4.8 × 10⁶), 1.14 × 10⁶ (4 × 10⁷), and 7.5 × 10⁵ (4.8 × 10⁵), respectively. Higher θ_angles and smaller fin heights generally result in higher RHE tolerances. Although decreasing the fin height reduced the RHE, it also decreased the on-current and resulted in an increase in the threshold voltage (V_T) and the subthreshold swing (SS). In addition, by increasing the substrate bottom doping concentration (P_{dop_bot}), we improve RHE tolerance twice its original level without reducing the on-current. Therefore, designing a buried channel array transistor (BCAT) structure requires careful consideration of these trade-offs, and a thorough understanding of the underlying mechanism is crucial to devising strategies that reduce RHE tolerance. The findings of this study are expected to contribute significantly to the development of next-generation DRAM architectures, enhancing stability and performance. By addressing the reliability challenges posed by advanced scaling, this study paves the way for the ongoing advancement of DRAM technology for high-density and high-performance applications.

Diode-type nand flash memory exhibits steep switching characteristics but is affected by grain boundary (GB) due to the polycrystalline silicon (poly-Si) channel. To determine the effects of these GBs, a single GB is placed under the cell where the positive feedback (PF) mechanism is triggered, and its positional influence on the turn-on voltage ( ${V}_{\text {on}}\text {)}$ under program (PGM) and erase (ERS) conditions is analyzed. In the PGM state, ${V}_{\text {on}}$ varies up to 650 mV depending on the GB location, while in the ERS state, it varies up to 300 mV. To reflect GB distributions, random Voronoi patterns are used, through which the multilevel cell (MLC) characteristics of diode-type and FET-type strings are compared. The mean and standard deviation ( $\sigma $ ) values of ${V}_{\text {on}}$ for the diode-type string are comparable to those of the FET-type string. As grain size (GS) increases, both structures show reduced subthreshold swing (SS), with the diode-type variant consistently exhibiting lower SS. For GS above 85 nm, the diode-type string also has lower $\sigma $ values of SS than the FET-type string. Depending on GS, the diode-type string maintains up to about $10^{{4}}$ times higher on/off ratio than the FET type string, enabling reliable data sensing during MLC operation. In addition, under temperature variations, the diode-type string exhibits comparable ${V}_{\text {on}}$ variation to the FET type string across different GSs, while maintaining lower SS and more stable on-current characteristics. These findings suggest that diode-type nand flash memory provides enhanced robustness and is a promising alternative for high-density applications such as triple-level cell (TLC) and quad-level cell (QLC).

To mimic the homeostatic functionality of biological neurons, a split-gate field-effect transistor (S-G FET) with a charge trap layer is proposed within a neuron circuit. By adjusting the number of charges trapped in the Si₃N₄ layer, the threshold voltage (V_th) of the S-G FET changes. To prevent degradation of the gate dielectric due to program/erase pulses, the gates for read operation and V_th control were separated through the fin structure. A circuit that modulates the width and amplitude of the pulse was constructed to generate a Program/Erase pulse for the S-G FET as the output pulse of the neuron circuit. By adjusting the V_th of the neuron circuit, the firing rate can be lowered by increasing the V_th of the neuron circuit with a high firing rate. To verify the performance of the neural network based on S-G FET, a simulation of online unsupervised learning and classification in a 2-layer SNN is performed. The results show that the recognition rate was improved by 8% by increasing the threshold of the neuron circuit fired.