The rapid expansion of data has made global access easier, but it also demands increasing amounts of energy for data storage and processing. In response, neuromorphic electronics, inspired by the functionality of biological neurons and synapses, have emerged as a growing area of research. These devices enable in-memory computing, helping to overcome the “von Neumann bottleneck”, a limitation caused by the separation of memory and processing units in traditional von Neumann architecture. By leveraging multi-bit non-volatility, biologically inspired features, and Ohm’s law, synaptic devices show great potential for reducing energy consumption in multiplication and accumulation operations. Within the various non-volatile memory technologies available, flash memory stands out as a highly competitive option for storing large volumes of data. This review highlights recent advancements in neuromorphic computing that utilize NOR, AND, and NAND flash memory. This review also delves into the array architecture, operational methods, and electrical properties of NOR, AND, and NAND flash memory, emphasizing its application in different neural network designs. By providing a detailed overview of flash memory-based neuromorphic computing, this review offers valuable insights into optimizing its use across diverse applications.

This study investigates the impact of four parameters—gate angles, fin height controlled through gate overlaps and the distance from fin to source/drain, and substrate bottom doping concentration—on the row hammer effect (RHE) in DRAM cells. The influence of adjacent and passing gates on the DRAM cell body potential was identified as a key factor in D0 and D1 failures. The tolerance for D1 and D0 failures was analyzed, defined as the threshold number of pulses required to induce a 0.6 V change in the storage node voltage (from 1.2 V to 0.6 V for a D1 failure or from 0 V to 0.6 V for a D0 failure). D1 (D0) failure tolerances with the slope from the top of the top gate (θ_angle) of 3°, the height of the TiN gate covering the fin (H_{fin_overlap}) of 12.5 nm, and the height of the fin (H_fin) of 12.5 nm are 1.26 × 10⁶ (4.8 × 10⁶), 1.14 × 10⁶ (4 × 10⁷), and 7.5 × 10⁵ (4.8 × 10⁵), respectively. Higher θ_angles and smaller fin heights generally result in higher RHE tolerances. Although decreasing the fin height reduced the RHE, it also decreased the on-current and resulted in an increase in the threshold voltage (V_T) and the subthreshold swing (SS). In addition, by increasing the substrate bottom doping concentration (P_{dop_bot}), we improve RHE tolerance twice its original level without reducing the on-current. Therefore, designing a buried channel array transistor (BCAT) structure requires careful consideration of these trade-offs, and a thorough understanding of the underlying mechanism is crucial to devising strategies that reduce RHE tolerance. The findings of this study are expected to contribute significantly to the development of next-generation DRAM architectures, enhancing stability and performance. By addressing the reliability challenges posed by advanced scaling, this study paves the way for the ongoing advancement of DRAM technology for high-density and high-performance applications.

An extended single-sided row hammer (ESH) attack—a novel variant of the row hammer vulnerability—is proposed for the first time in 10 nm-class dynamic random-access memory (DRAM). This method enhances the single-sided row hammer (SH) technique by utilizing a transfer line to induce bit flips in memory cells that are not directly adjacent to the aggressor row. Unlike the double-sided row hammer (DH), which applies repeated pulses to both neighboring word lines of a victim row, the proposed ESH mechanism can induce bit flips with relatively fewer pulses on an adjacent word line, thereby disturbing cells beyond the immediate neighbors. Furthermore, the influence of interface trap density (D_it) at the silicon fin–trench oxide interface is investigated as a key factor affecting the severity of ESH attacks. Simulation results demonstrate that a higher D_it intensifies the lateral electric field and increases electron current density, thereby accelerating charge loss in the memory node. 3D TCAD simulations confirm that these amplified electrical effects exacerbate ESH-induced bit flips. These findings underscore the necessity for novel refresh schemes capable of addressing indirect disturbance mechanisms in DRAM systems.

Diode-type nand flash memory exhibits steep switching characteristics but is affected by grain boundary (GB) due to the polycrystalline silicon (poly-Si) channel. To determine the effects of these GBs, a single GB is placed under the cell where the positive feedback (PF) mechanism is triggered, and its positional influence on the turn-on voltage ( ${V}_{\text {on}}\text {)}$ under program (PGM) and erase (ERS) conditions is analyzed. In the PGM state, ${V}_{\text {on}}$ varies up to 650 mV depending on the GB location, while in the ERS state, it varies up to 300 mV. To reflect GB distributions, random Voronoi patterns are used, through which the multilevel cell (MLC) characteristics of diode-type and FET-type strings are compared. The mean and standard deviation ( $\sigma $ ) values of ${V}_{\text {on}}$ for the diode-type string are comparable to those of the FET-type string. As grain size (GS) increases, both structures show reduced subthreshold swing (SS), with the diode-type variant consistently exhibiting lower SS. For GS above 85 nm, the diode-type string also has lower $\sigma $ values of SS than the FET-type string. Depending on GS, the diode-type string maintains up to about $10^{{4}}$ times higher on/off ratio than the FET type string, enabling reliable data sensing during MLC operation. In addition, under temperature variations, the diode-type string exhibits comparable ${V}_{\text {on}}$ variation to the FET type string across different GSs, while maintaining lower SS and more stable on-current characteristics. These findings suggest that diode-type nand flash memory provides enhanced robustness and is a promising alternative for high-density applications such as triple-level cell (TLC) and quad-level cell (QLC).

In the era of big data, robust data security is more critical than ever. One promising way to create unpredictable random keys is to use the intrinsic physical randomness of electronic devices. However, controlling and reproducing this randomness remains a significant challenge. For the first time, we reveal a parabolic input-output relationship enabled by the band-to-band tunneling (BTBT) mechanism in a positive feedback transistor (PFT). By applying iterative operations, we observe chaotic bifurcation behavior, which allows the stable generation of analog random values across more than 10¹⁰ cycles. These random values are then used to encrypt and decrypt images, showcasing how encryption technologies can be implemented with just a single PFT. We also show that the charge-trap flash memory (CTF) array integrated with the PFTs can store encrypted information. This study highlights the potential of PFTs as random key generators and examines the device’s behavior under chaotic conditions. By leveraging the physical characteristics of the device, we provide a secure and reliable method for data encryption.