We present a circuit-compatible compact model of the intrinsic capacitances of GFETs. Together with a compact drain current model, a large-signal model is developed combining both models as a tool for simulating the electrical behavior of graphene-based integrated circuits, dealing with the dc, transient behavior, and frequency response of the circuit. The drain current model is based on a drift-diffusion mechanism for the carrier transport coupled with an appropriate field-effect approach. The intrinsic capacitance model consists of a 16-capacitance matrix including self-capacitances and transcapacitances of a four-terminal GFET. To guarantee charge conservation, a Ward–Dutton linear charge partition scheme has been used. The large-signal model has been implemented in Verilog-A, being compatible with conventional circuit simulators and serving as a starting point toward the complete GFET device model that could incorporate additional nonidealities.

The progress made toward the definition of a modular compact modeling technology for graphene field‐effect transistors (GFETs) that enables the electrical analysis of arbitrary GFET‐based integrated circuits is reported. A set of primary models embracing the main physical principles defines the ideal GFET response under DC, transient (time domain), AC (frequency domain), and noise (frequency domain) analysis. Another set of secondary models accounts for the GFET non‐idealities, such as extrinsic‐, short‐channel‐, trapping/detrapping‐, self‐heating‐, and non‐quasi static‐effects, which can have a significant impact under static and/or dynamic operation. At both device and circuit levels, significant consistency is demonstrated between the simulation output and experimental data for relevant operating conditions. Additionally, a perspective of the challenges during the scale up of the GFET modeling technology toward higher technology readiness levels while drawing a collaborative scenario among fabrication technology groups, modeling groups, and circuit designers, is provided.

A small-signal equivalent circuit of 2D-material based FETs is presented. Charge conservation and nonreciprocal capacitances have been assumed, so the model can be used to make reliable predictions at both device and circuit levels. In this context, explicit and exact analytical expressions of the main radio-frequency figures of merit of these devices are given. Moreover, a direct parameter extraction methodology is provided based on S-parameter measurements. In addition to the intrinsic capacitances, transconductance and output conductance, our approach allows extracting the series combination of drain-source metal contact and access resistances. Accounting for these extrinsic resistances is of upmost importance when dealing with low dimensional FETs.

This paper presents a circuit performance benchmarking using the large-signal model of graphene FET reported in Part I of this two-part paper. To test the model, it has been implemented in a circuit simulator. In particular, we have simulated a high-frequency performance amplifier, together with other circuits that take the advantage of the ambipolarity of graphene, such as a frequency doubler, an RF subharmonic mixer, and a multiplier phase detector. A variety of simulations comprising dc, transient dynamics, Bode diagram, S parameters, and power spectrum have been compared with experimental data to assess the validity of the model.

We present a graphene-based phase shifter for radio-frequency (RF) phase-array applications. The core of the designed phase-shifting system consists of a graphene field-effect transistor (GFET) used in a common source amplifier configuration. The phase of the RF signal is controlled by exploiting the quantum capacitance of graphene and its dependence on the terminal transistor biases. In particular, by independently tuning the applied gate-to-source and drain-to-source biases, we observe that the phase of the signal, in the super-high frequency band, can be varied nearly 200° with a constant gain of 2.5 dB. Additionally, if only the gate bias is used as control signal, and the drain is biased linearly dependent on the former (i.e., in a completely analogue operation), a phase shift of 85° can be achieved making use of just one transistor and keeping a gain of 0 dB with a maximum variation of 1.3 dB. The latter design can be improved by applying a balanced branch-line configuration showing to be competitive against other state-of-the-art phase shifters. This work paves the way towards the exploitation of graphene technology to become the core of active analogue phase shifters for high-frequency operation.

We present a physics-based circuit-compatible model for double-gated two-dimensional semiconductor-based field-effect transistors, which provides explicit expressions for the drain current, terminal charges, and intrinsic capacitances. The drain current model is based on the drift-diffusion mechanism for the carrier transport and considers Fermi–Dirac statistics coupled with an appropriate field-effect approach. The terminal charge and intrinsic capacitance models are calculated adopting a Ward–Dutton linear charge partition scheme that guarantees charge conservation. It has been implemented in Verilog-A to make it compatible with standard circuit simulators. In order to benchmark the proposed modeling framework we also present experimental DC and high-frequency measurements of a purposely fabricated monolayer MoS₂-FET showing excellent agreement between the model and the experiment and thus demonstrating the capabilities of the combined approach to predict the performance of 2DFETs.