Hybrid AC/DC microgrids (HMGs) are increasingly recognized as a solution for the transition toward future energy systems because they can combine the efficiency of DC networks with an AC system. Despite these advantages, HMGs still have challenges in protection, cybersecurity, and reliability. Conventional protection schemes often fail due to reduced fault currents and the dominance of power electronic converters in islanded or dynamically reconfigured topologies. At the same time, IEC 61850 protocols remain vulnerable to advanced cyberattacks such as Denial of Service (DoS), false data injection (FDIA), and man-in-the-middle (MITM), posing serious threats to the stability and operational security of intelligent power networks. Previous surveys have typically examined these challenges in isolation; however, this paper provides the first integrated review of HMG protection across three complementary dimensions: traditional protection schemes, cybersecurity threats, and artificial intelligence/machine learning (AI/ML)-based approaches. By analyzing more than 100 studies published between 2012 and 2024, we show that AI/ML methods in simulation environments can achieve detection accuracies of 95–98% with response times under 10 ms, while these values are case-specific and depend on the evaluation setting such as network scale, sampling configuration, noise levels, inverter control mode, and whether results are obtained in simulation, hardware in loop (HIL)/real-time digital simulator (RTDS), or field conditions. Nevertheless, the absence of standardized datasets and limited field validation remain key barriers to industrial adoption. Likewise, existing cybersecurity frameworks provide acceptable protection timing but lack resilience against emerging threats, while conventional methods underperform in clustered and islanded scenarios. Therefore, the future of HMG protection requires the integration of traditional schemes, resilient cybersecurity architectures, and explainable AI models, along with the development of benchmark datasets, hardware-in-the-loop validation, and implementation on platforms such as field-programmable gate array (FPGA) and μPMU.

A high performance bulk-driven rail-to-rail fully differential buffer operating from ±0.3V supplies in 180 nm CMOS technology is reported. It has a differential–difference input stage and common mode feedback circuits implemented with no-tail, high CMRR bulk-driven pseudo-differential cells. It operates in subthreshold, has infinite input impedance, low output impedance (1.4 kΩ), 86.77 dB DC open-loop gain, 172.91 kHz bandwidth and 0.684 μW static power dissipation with a 50-pF load capacitance. The buffer has power efficient class AB operation, a small signal figure of merit FOM_SS = 12.69 MHzpFμW⁻¹, a large signal figure of merit FOM_LS = 34.89 (V/μs) pFμW⁻¹, CMRR = 102 dB, PSRR+ = 109 dB, PSRR− = 100 dB, 1.1 μV/√Hz input noise spectral density, 0.3 mVrms input noise and 3.5 mV input DC offset voltage.

The application of the flipped voltage follower to implement two high-performance circuits is presented: (1) The first is a class AB cascode flipped voltage follower that shows an improved slew rate and an improved bandwidth by very large factors and that has a higher output range than the conventional flipped voltage follower. It has a small signal figure of merit FOM_SS = 46 MHz pF/µW and a current efficiency figure of merit FOM_CE = 118. This is achieved by just introducing an additional output current sourcing PMOS transistor (P-channel Metal Oxide Semiconductor Field Effect Transistor) that provides dynamic output current enhancement and increases the quiescent power dissipation by less than 10%. (2) The other is a high-performance low-voltage current mirror with a nominal gain accuracy better than 0.01%, 0.212 Ω input resistance, 112 GΩ output resistance, 1 V supply voltage requirements, 0.15 V input, and 0.2 V output compliance voltages. These characteristics are achieved by utilizing two auxiliary amplifiers and a level shifter that increase the power dissipation just moderately. Post-layout simulations verify the performance of the circuits in a commercial 180 nm CMOS (Complementary Metal Oxide Semiconductor) technology.

A three‐stage rail‐to‐rail bulk‐driven class AB OTA that operates with ±0.15 V supplies and a power dissipation of 90 nW is introduced. The first two stages use resistive local common mode feedback. The OTA uses simple phase lead compensation. It has a 36 MHz.pF/μW small signal figure of merit and a 55(V/μs) pF/μW large signal figure of merit.

Solid-state transformers (SSTs) are pivotal for next-generation power systems, yet their widespread adoption is hindered by reliability uncertainties under diverse operational conditions. This paper introduces a mission-profile-aware, physics-of-failure (PoF) reliability assessment framework that explicitly links operating conditions, degradation mechanisms, and statistical uncertainty. The approach combines PoF models for stress-sensitive components with handbook-based reliability models for passive elements, employing Joint Electron Device Engineering Council (JEDEC)-aligned statistical methods for failure rate extraction. Quantitative failure-in-time (FIT) estimates are integrated into a physics-informed Failure mode and effects analysis (FMEA), replacing subjective occurrence rankings with FIT-derived quantitative occurrence ratings while retaining explicit severity and detection criteria. The framework is demonstrated on a 10 kW Type-IV SST across multiple mission profiles and ambient temperatures. The results reveal that the system-level mean time between failures (MTBF) varies from 4.6 to over 8 years, with gate-driver electronics and DC-link capacitors dominating FIT contributions. Mission-dependent shifts in failure mechanisms highlight the inadequacy of single MTBF metrics. This scalable framework provides a foundation for reliability-oriented SST design, qualification, and deployment.