Perimeter detection systems detect intruders penetrating protected areas, but modern solutions require the combination of smart detectors, information networks and controlling software to reduce false alarms and extend detection range. The current solutions available to secure a perimeter (infrared and motion sensors, fiber optics, cameras, radar, among others) have several problems, such as sensitivity to weather conditions or the high failure alarm rate that forces the need for human supervision. The system exposed in this paper overcomes these problems by combining a perimeter security system based on CEMF (control of electromagnetic fields) sensing technology, a set of video cameras that remain powered off except when an event has been detected. An autonomous drone is also informed where the event has been initially detected. Then, it flies through computer vision to follow the intruder for as long as they remain within the perimeter. This paper covers a detailed view of how all three components cooperate in harmony to protect a perimeter effectively, without having to worry about false alarms, blinding due to weather conditions, clearance areas, or privacy issues. The system also provides extra information of where the intruder is or has been, at all times, no matter whether they have become mixed up with more people or not during the attack.

Reduction of minimum supply requirements is a crucial aspect to decrease the power consumption in VLSI systems. A high-performance capacitance multiplier able to operate with supplies as low as ± 0.25 V is presented. It is based on adaptively biased class-AB current mirrors which provide high current efficiency. Measurement results of a factor 11 capacitance multiplier fabricated in 180-nm CMOS technology verify theoretical claims. Moreover, low-voltage precision rectifiers based on the same class-AB current mirrors are designed and fabricated in the same CMOS process. They generate output currents over 100 times larger than the quiescent current. Both proposed circuits have 300-nW static power dissipation when operating with ± 0.25-V supplies.

The application of the flipped voltage follower to implement two high-performance circuits is presented: (1) The first is a class AB cascode flipped voltage follower that shows an improved slew rate and an improved bandwidth by very large factors and that has a higher output range than the conventional flipped voltage follower. It has a small signal figure of merit FOM_SS = 46 MHz pF/µW and a current efficiency figure of merit FOM_CE = 118. This is achieved by just introducing an additional output current sourcing PMOS transistor (P-channel Metal Oxide Semiconductor Field Effect Transistor) that provides dynamic output current enhancement and increases the quiescent power dissipation by less than 10%. (2) The other is a high-performance low-voltage current mirror with a nominal gain accuracy better than 0.01%, 0.212 Ω input resistance, 112 GΩ output resistance, 1 V supply voltage requirements, 0.15 V input, and 0.2 V output compliance voltages. These characteristics are achieved by utilizing two auxiliary amplifiers and a level shifter that increase the power dissipation just moderately. Post-layout simulations verify the performance of the circuits in a commercial 180 nm CMOS (Complementary Metal Oxide Semiconductor) technology.

The front-end readout channel consists of a charge sensitive amplifier (CSA) and two different unipolar-shaping circuits to generate pulses suitable for time and energy measurement. The signal processing chain of the single channel is built of two different parallel processing paths: a fast path with a peaking time of 30 ns to obtain the time of arrival for each particle impinging the detector; and a slow path with a peaking time of 400 ns dedicated for low noise amplitude measurements, which is formed by a pole-zero cancellation circuit and a 4th order complex shaper based on a bridged-T architecture. The tunability of the system is accomplished by the discharge time constant of the CSA in order to accommodate various event rates. The readout system has been implemented in a 180 nm CMOS technology with the size of 525 $\mu \text{m}$ x $290~\mu \text{m}$ . The building blocks use compact gain-boosting techniques based on quasi-floating gate (QFG) transistors achieving accurate energy measurement with good resolution. The high impedance nodes of QFG transistors require a detailed study of sensitivity to single-effect transients (SET). After carrying out this study, this paper proposes a method to select the value of the QFG capacitors, minimizing the area occupancy while maintaining robustness to radiation. The nonlinearity of the CSA-slow-shaper has been found to be less than 1% over a 10–70 fC input charge. The power dissipation of the readout channel is 4.1 mW with a supply voltage of 1.8 V.