This paper presents a low power, all-digital multichannel Time to Digital Converter (TDC) for Light Detection and Ranging (LiDAR) sensors. The proposed TDC architecture here, measures the time interval through a coarse counter, middle, and fine delay line based interpolation technique (the Nutt method). Automatic calibration by middle and fine All Digital Delay Locked Loops (ADDLL) is provided to ensure the stability of the generated time-slots. Charge pump, loop filter, and voltage-controlled delay line inside the conventional analog Delay Locked Loops (DLL) are replaced by an Accumulator (ACC) and Digitally Controlled Delay Line (DCDL). This makes the design particularly compact, low power, and suitable for multichannel applications. The presented architecture can generate information for amplitude variation (Walk Error) compensation. This information is generated by measuring the pulse width and position of three successive STOP pulses inside each channel within a single-shot measurement. A low-jitter Injection Locked Frequency Multiplier (ILFM) generates 625 MHz internal clock signal out of 25 MHz external reference oscillator, which shrinks the number of delay elements to cover one period of the reference clock and improves the precision of the TDC. Operation at higher frequency provides high throughput and short conversion time (less than 3ns). The three-level TDC offers 13.1 μs maximum input range and 50 ps resolution. The measured DNL and INL of the TDC circuit are 0.47 and 0.71 LSB, respectively. The TDC circuit is implemented in a 180 nm standard CMOS process with a die size of 1.5 mm × 1.5 mm. The total power consumption of the multichannel TDC is 87.6 mW.

This paper presents a wide-range and low phase noise mm-Wave Voltage Controlled Oscillator (VCO) based on the transconductance linearization technique. The proposed technique eliminates the deep triode region of the active part of the VCO, and lowers the noise introduced by the g_m-cell. The switch sizes inside the switched capacitor bank of the VCO are optimized to minimize the resistance of the switches while keeping the wide tuning range. A new layout technique shortens the routing of the VCO outputs, and lowers the parasitic inductance and resistance of the VCO routing. The presented method prevents the reduction of the quality factor of the tank due to the long routing. The proposed VCO achieves a discrete frequency tuning range, of 14 GHz to 18 GHz, through a linear coarse and middle switched capacitor array, and offers superior phase noise performance compared to recent state-of-the-art VCO architectures. The design is implemented in a 45 nm CMOS process and occupies a layout area (including output buffers) of 0.14 mm². The power consumption of the VCO core is 24 mW from the power supply of 0.8 V. The post-layout simulation result shows the VCO achieves the phase noise performances of −87.2 dBc/Hz and −113 dBc/Hz, at 100 kHz and 1 MHz offset frequencies from the carrier frequency of 14 GHz, respectively. In an 18 GHz carrier frequency, the results are −87.4 dBc/Hz and −110 dBc/Hz, accordingly.

This paper presents a duty cycle-based, dual-mode simultaneous wireless information and power transceiver (SWIPT) for Internet of Things (IoT) devices in which a sensor node monitors the received power and adaptively controls the single-tone or multitone communication mode. An adaptive power-splitting (PS) ratio control scheme distributes the received radio frequency (RF) energy between the energy harvesting (EH) path and the information decoding (ID) path. The proposed SWIPT enables the self-powering of an ID transceiver above 20 dBm input power, leading to a battery-free network. The optimized PS ratio of 0.44 enables it to provide sufficient harvested energy for self-powering and energy-neutral operation of the ID transceiver. The ID transceiver can demodulate the amplitude-shift keying (ASK) and the binary phase-shift keying (BPSK) signals. Moreover, for low-input power level, a peak-to-average power ratio (PAPR) scheme based on multitone is also proposed for demodulation of the information-carrying RF signals. Due to the limited power, information is transmitted in uplink by backscatter modulation instead of RF signaling. To validate our proposed SWIPT architecture, a SWIPT printed circuit board (PCB) was designed with a multitone SWIPT board at 900 MHz. The demodulation of multitone by PAPR was verified separately on the PCB. Results showed the measured sensitivity of the SWIPT to be −7 dBm, and the measured peak power efficiency of the RF energy harvester was 69% at 20 dBm input power level. The power consumption of the injection-locked oscillator (ILO)-based phase detection path was 13.6 mW, and it could be supplied from the EH path when the input power level was high. The ID path could demodulate 4-ASK- and BPSK-modulated signals at the same time, thus receiving 3 bits from the demodulation process. Maximum data rate of 4 Mbps was achieved in the measurement.

This article presents a 2.4 GHz and high-efficiency wireless power receiver (Rx) integrated with a low-power transmitter (Tx) for wireless charging of the Internet-of-Things (IoT) or wearable devices. A single pole double throw (SPDT) circuit isolates the operation of the Rx from Tx, thereby offering the capability of sharing antenna between them. The Rx employs a high-efficiency radio frequency (RF)-dc converter, which is facilitated with threshold voltage cancellation technique for enhancing the efficiency, and adjustable internal impedance matching network to compensate the nonlinear behavior of the input impedance with respect to input power level. In addition, it includes a boost dc-dc converter to charge the storage element with a fixed voltage and current. The Tx utilizes a low-power phase-locked loop (PLL) and a class-D power amplifier (PA). Several techniques are adopted to achieve low power consumption. The chip is implemented in a 180 nm CMOS process with a die size of $2.3\,\,\mathrm {mm} \times 5\,\,\mathrm {mm}$ . The Rx shows the measured RF to dc maximum power conversion efficiency (PCE) of 53.8% at the input power level of 0 dBm. The Tx achieves a variable output power range of −10 to 10 dBm, while consumes 4 and 23 mA at 0 and 10 dBm output power, respectively.

This paper presents a second-order discrete-time Sigma-Delta (SD) Analog-to-Digital Converter (ADC) with over 80 dB Signal to Noise Ratio (SNR), which is applied in a signal conditioning IC for automotive piezo-resistive pressure sensors. To reduce the flicker noise of the structure, choppers are used in every stage of the high gain amplifiers. Besides, to reduce the required area and power, only the CIC filter structure is adopted as a decimation filter. This filter has a configurable structure that can be applied to different data rates and input signal bandwidths. The proposed ADC was fabricated and measured in a 0.18-µm CMOS process. Due to the application of only a CIC filter, the total active area of the SD-ADC and reference generator is 0.49 mm² where the area of the decimation filter is only 0.075 mm². For the input signal bandwidth of 1.22 kHz, it achieved over 80 dB SNR in a 2.5 MHz sampling frequency while consuming 646 µW power.