This paper presents a three-segment interpolating Digital-to-Analog Converter (DAC) that employs a redundancy-based interpolation scheme and digital calibration to enhance linearity. The proposed architecture consists of a Most Significant Bit (MSB) resistor string DAC, an Intermediate Significant Bit (ISB) resistor string DAC, and a Least Significant Bit (LSB) interpolating differential buffer. The MSB segment uses a split-unit resistor structure ($r_A,r_B$) to improve post-calibration differential nonlinearity (DNL) by minimizing voltage step errors. A fully digital calibration algorithm is implemented to compensate for process variations, component mismatches, and finite switch resistance, ensuring a highly linear DAC output. The proposed 16-bit DAC is implemented in a 180 nm CMOS process and is segmented into a 5-bit MSB stage, a 5-bit ISB stage, and a 6-bit LSB stage. The structure achieves post-calibration integral nonlinearity (INL) and differential nonlinearity (DNL) values of less than ±1 LSB. Simulation results validate the proposed design, demonstrating enhanced linearity and reduced area overhead compared with conventional segmented architectures.

Distributed measurement networks, from semiconductor testing arrays to environmental sensor grids, medical diagnostic systems, and agricultural monitoring stations, face a fundamental challenge: undetected site-to-site variations that silently corrupt data integrity. These variations create systematic biases between supposedly identical measurement units, which undermine scientific reproducibility and yield. The current site-to-site variation detection methods require extensive sampling or make rigid distributional assumptions, making them impractical for many applications. We introduce a novel framework that transforms measurement data into density-based feature vectors using Kernel Density Estimation, followed by anomaly detection with Isolation Forest. To automate the final classification, we then apply a novel probabilistic thresholding method using Gaussian Mixture Models, which removes the need for user-defined anomaly proportions. This approach identifies problematic measurement sites without predefined anomaly proportions or distributional constraints. Unlike traditional methods, our method works efficiently with limited samples and adapts to diverse measurement contexts. We demonstrate its effectiveness using semiconductor multisite testing as a case study, where our approach consistently outperforms state-of-the-art methods in detection accuracy and sample efficiency when validated against industrial testing environments.

This paper presents a precision, wide-dynamic-range leakage current sensor tailored for in-situ monitoring of aging mechanisms such as Time-Dependent Dielectric Breakdown (TDDB) in both active and passive components. The proposed architecture supports high-voltage stress and is fully monolithic, integrating a current-to-voltage front-end, tunable-gain amplifier, and a successive approximation register (SAR) analog-to-digital converter (ADC). To validate the concept, a discrete-component prototype was implemented and evaluated across a leakage current range of 1 nA to 1 $\mathsf{\mu }$A. The sensor achieves 12-bit resolution with measured integral non-linearity (INL) and differential non-linearity (DNL) within $\pm 1.5$ LSB and $\pm 0.3$ LSB, respectively. Compared to prior monitors, the design enables linear current digitization and supports high-voltage stress, features essential for accurate and scalable TDDB characterization. Applications include embedded reliability monitoring in power converters, analog building blocks, and large-scale aging test arrays.

This paper presents a precision, wide-dynamic-range leakage current sensor tailored for in-situ monitoring of aging mechanisms such as Time-Dependent Dielectric Breakdown (TDDB) in both active and passive components. The proposed architecture supports high-voltage stress and is fully monolithic, integrating a current-to-voltage front-end, tunable gain amplifier, and a successive approximation register (SAR) analog-to-digital converter (ADC). To validate the concept, a discrete-component prototype was implemented and evaluated across a leakage current range of 1nA to 1 μA. The sensor achieves 12-bit resolution with measured integral nonlinearity (INL) and differential nonlinearity (DNL) within ±1.5 LSB and ±0.3 LSB, respectively. Compared to prior monitors, the design enables linear current digitization and compatibility with high-voltage stress, features essential for accurate and scalable TDDB characterization. Applications include embedded reliability monitoring in power converters, analog building blocks, and large-scale aging test arrays.