The aim of this paper is the analysis of voltage spikes arising at the gate-source terminals during the commutation of Silicon Carbide (SiC) MOSFET Power Devices. The voltage spikes are noticed in a half bridge configuration and they can be appreciated when a SiC MOSFET is in off state while its complementary is PWM commutated. The influence of the device technology and its packaging on these transient overvoltages has been properly modeled including internal device and board parasitics. Moreover, wide experimental tests campaign have been performed highlighting pros and cons of different device packages.

The main aim of this work is to present a step-by-step procedure to model and analyze the power loss distribution of three-level Gallium Nitride (GaN) inverters. It has been applied to three distinct three-phase three-level voltage source inverters utilized in electric traction drives: Active Neutral Point Clamped, Neutral Point Clamped and T-Type Neutral Point Clamped. The proposed analytical power loss modelling, combined with an equivalent representation of the electrical machine proved to be a viable solution to achieve a time-saving and low computational burden simulation platform, leading to satisfying accurate results. This has been confirmed by comparing the results carried out from the simulations of a 110 kW permanent magnet synchronous motor drive and those determined by considering a simplified circuital representation based on the proposed analytical power loss modelling.

This paper investigates the behavior of SiC MOSFETs body diode reverse recovery as a function of different operating conditions. The knowledge of their effects is crucial to properly designing and driving power converters based on SiC devices, in order to optimize the MOSFETs commutations aiming at improving efficiency. Indeed, reverse recovery is a part of the switching transient, but it has a significant role due to its impact on recovery energy and charge. The set of different operating conditions has been properly chosen to prevent or force the snappy recovery of the device under testing. The experimental results and specific software simulations have revealed phenomena unknown in the literature. More specifically, the analysis of the reverse recovery charge, Q_rr, revealed two unexpected phenomena at high temperatures: it decreased with increasing gate voltage; the higher the device threshold, the higher the Q_rr. TCAD-Silvaco (ATLAS v. 5.29.0.C) simulations have shown that this is due to a displacement current flowing in the drift region due to the output capacitance voltage variation during commutation. From the analysis of the snappy recovery, it has emerged that there is a minimum forward current slope, below which the reverse recovery cannot be snappy, even for a high current level. Once this current slope is reached, Q_rr varies with the forward current only.

Measuring the gate-source voltages of wide bandgap (WBG) devices in half-bridge converters provides useful information about susceptibility to crosstalk, which can cause uncontrolled cross-conduction and excessive gate-oxide stresses. However, parasitic elements of the printed circuit board (PCB) and device packaging can compromise measurement accuracy, causing unreliable results. Here we describe how this shortcoming can be addressed using devices in packages that have a Kelvin source pin, allowing a more accurate analysis.

Silicon carbide (SiC) power converters are attracting increasing interest due to their significant advantages in terms of efficiency, switching speed, and greater temperature tolerance compared to traditional silicon-based converters. Tools to improve the design process, such as those to predict the switching behavior of silicon carbide-based power converters, can be of great help, e.g., in studying critical electrical/thermal stress in power devices. This work aims to present an effective multi-objective optimization method to identify the main parasitic parameters of a SiC half-bridge power converter related to the board layout and device packaging. This goal was achieved by minimizing the errors between the system responses carried out by the simulated power converter and the measurements collected from a limited number of experimental tests. The feasibility and effectiveness of the method are verified by tests performed on a 1200 V, 75 A, SiC half-bridge converter. Although this methodology has been validated for a specific converter topology, it can be extended to model more complex power converter structures.

The main aim of this work is to present a step-by-step procedure to model and analyze the power loss distribution of three-level Gallium Nitride (GaN) inverters. It has been applied to three distinct three-phase three-levels voltage source inverters utilized in electric traction drives: Active Neutral Point Clamped, Neutral Point Clamped and T-Type Neutral Point Clamped. The proposed analytical power loss modelling, combined to an equivalent representation of the electrical machine demonstrated to be a viable solution to achieve a time-saving and low computational burden simulation platform, leading to satisfying accuracy results. This has been confirmed by comparing the results carried out from the simulations of a 110kW permanent magnet synchronous motor drive and those determined by considering a simplified circuital representation based on the proposed analytical power loss modelling.