This paper presents the design and implementation of a 64-Multi-Phased Time-to-Digital Converter (TDC64) architecture on a low-cost Cyclone V FPGA. Operating at 500 MHz, the architecture successfully achieves a theoretical resolution of 31.25 picoseconds (ps). The modular design leverages a multi-phased counter methodology to significantly enhance temporal granularity. The performance was comprehensively characterized in two stages. Internal analysis, using the Signal Tap Logic Analyzer, confirmed the design's integrity, yielding a measurement result of 9660 for a 300 ns interval, representing a low deviation of approximate 0.62 %. Linearity tests conducted over a 20 ns span showed excellent performance with differential nonlinearity (DNL) ranging from +0.053 to -0.101 and integral nonlinearity (INL) between -0.192 and -0.218. External testing, utilizing a waveform generator and oscilloscope, revealed an uncompensated resolution of 47.43 ps (34 % deviation). Mitigating the noise, the compensated resolution for an interval of 300 ns result in 9,596, a resolution of 31.263 picoseconds, which represents 0.04%. A remarkable result close to the theoretically expected value. The mean values were employed to evaluate the linearity, yielding DNL of +0,0560 and -0,0129, as well as INL of +0,0484 and -0,2104. Representing high linearity and high resolution compared with a previous noisy entry signal. This work demonstrates that high-end timing performance is attainable on cost-effective FPGA platforms.

This paper reports a statistical analysis of n-channel MOSFETs fabricated in a commercial 350 nm Bulk CMOS technology, quantifying the impact of the Diamond (hexagonal-gate) layout style relative to the conventional Rectangular MOSFET (RM) under high-dose ⁶⁰Co gamma irradiation. Devices with both layout styles were designed with identical aspect ratios (W/L) and gate areas and subjected to cumulative Total Ionizing Dose (TID) levels up to 1.814 Mrad following MIL-STD-883 and ESA-22900 standards, using a ⁶⁰Co source at 1 krad (Si)/h under worst-case on-state bias. The Diamond MOSFET (DM) with α = 90° exhibited superior radiation tolerance. The coefficients of variation of threshold voltage (VTH) and subthreshold slope (SS) were reduced by 45% and 59%, respectively. The DM sustained a negligible TID-induced VTH shift, remaining the only layout free of a net negative shift, in contrast to a -550 mV degradation observed for the RM at 1.814 Mrad. Furthermore, the DM confined the leakage-current (ILEAK) increase to less than 0.5 decades versus 3.5 decades for the RM, while preserving the ION/IOFF ratio within one order of magnitude, versus 3.7 decades for the RM. These improvements are attributed to the Deactivation of Parasitic MOSFETs in the Bird's Beak Regions Effect (DEPAMBBRE), whose interplay with the Longitudinal Corner Effect (LCE) and the Parallel Association of MOSFETs with Different Channel Lengths Effect (PAMDLE) governs the angular dependence of radiation hardness. These findings establish the Diamond layout as an effective, area-efficient Radiation-Hardness-By-Design (RHBD) strategy for high-reliability CMOS ICs in space, nuclear, military, and medical applications.

This work performs an experimental comparative study of the impact of X-rays ionizing radiation on the matching properties between Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), n-channel, which were implemented with octagonal (Octo MOSFET, OnM) and conventional (Conventional MOSFET, CnM) layout styles. The primary objective was to validate the superior stability of the octagonal geometry under the Total Ionizing Dose (TID) effects. Statistical techniques, including Z-score standardization, K-means clustering, and Hierarchical Clustering (Ward's Method), were employed to analyze the electrical parameters related to the saturation drain current (IDSsat), maximum transconductance (gm_max), and analogy efficiency (gm_max/I_DSsat). The clustering methodology objectively quantified the difference in ionizing radiation response and characterized device variability, confirming the structural separation of the data. The results indicate statistically significant differences in these parameters between the devices. Notably, the matching between devices for the OnMs presents an X-ray radiation tolerance 1.742 times better than that measured for the matching between CnMs, demonstrating lower variability and greater stability. This lower dispersion is further supported by the Coefficient of Variation ( ), which was significantly lower for the OnM devices (e.g., : 1.9% compared to 2.8%). For advanced validation, a refined Logistic Regression model was developed, achieving 100 % accuracy in classifying the device layout based on gmmax and IDSsat values. The model quantified the predictive electrical signature of robustness, confirming that gmmax is the dominant predictive factor (with a coefficient approximately 7 times larger than IDSsat) in separating the two groups. Therefore, the octagonal layout style for MOSFETs can be considered an alternative strategy to enhance radiation-hardened-by-design (RHBD) capabilities, with a primary focus on analog and radiofrequency Complementary MOS (CMOS) integrated circuit (IC) applications.

Conventional undergraduate computer architecture curricula typically prioritize microarchitectural theory validated solely through logic simulation, often omitting the complex engineering layers required for physical hardware deployment and high-level language execution. This work addresses this disparity by presenting the end-to-end design, implementation, and physical validation of a fully functional RISC-V (RV32I) soft-core processor targeting the Intel Cyclone V FPGA. To bridge the gap between pedagogical models and operational embedded systems, the project adopts a rigorous engineering methodology encompassing a containerized toolchain for cross-platform reproducibility, a robust memory mapped I/O architecture, and a multi-tiered verification strategy leveraging GHDL, Cocotb, and the RISC-V Architectural Compliance Suite (RISCOF). By integrating vendor-specific Intellectual Property (IP) for memory management and clock distribution, the design resolves critical timing and signal integrity constraints often overlooked in educational settings. The resulting implementation achieves a maximum operating frequency (Fmax) of 123.4 MHz with a minimal logic footprint of only 9% ALM utilization, successfully executing bare-metal C applications. These results demonstrate that applying industrial- grade verification and synthesis workflows transforms academic prototypes into reliable, deployable hardware.