With the electrification of society and the green transition, the need for efficient high-power electronic converters to support the electricity demand is at an all-time high. A key enabler is the emerging medium voltage (MV) silicon-carbide (SiC) semiconductor devices, which offer improved static and dynamic performance compared to their silicon-counterparts. This article presents a thorough overview of the recent advancements within the MV SiC technology, examining both available semiconductor devices and power modules from industry and academia and directly associates them to their applicability through a comprehensive review of typical high-power electronic applications. At last, the future perspectives on the applicability and commercial widespread of the MV SiC technology are presented.

Recent developments within the field of medium voltage wide-bandgap semiconductor devices are drawing attention from both researchers and industries due to the demanding requirements for more efficient high-power energy conversion. The rapid development has entailed an increased awareness of the negative impact of the increased rate of change in voltage, d v /d t , and its derived issues caused by the inevitable parasitic capacitive couplings. This article is dedicated to present an overview of the parasitic capacitive couplings in high-power medium voltage power electronic converter systems, using an example reference system enabled by medium voltage SiC mosfet s. The definitions of capacitive couplings are presented and the impacts raised by parasitic capacitive couplings are reviewed. In addition, the similarities of different capacitive couplings introduced by components in practical medium voltage systems are presented and summarized. Lastly, the challenges and future work with respect to parasitic capacitive couplings in medium voltage power electronics converter systems are shared from the authors' perspective.

With the development of wide band-gap devices, Silicon Carbide (SiC) semiconductor devices in 10–15 kV voltage class offer potentials in medium-voltage (MV) systems. To ensure the reliable operation of these MV SiC devices, gate driver power supplies must meet specific requirements: MV isolation capability, low coupling capacitance, stable performance across fluctuating voltage potentials, and assembly convenience. This article proposes a customized gate driver power supply solution. The proposed core-series-coupling planar transformer meets the specified requirements and significantly reduces common-mode capacitance by series connection of core, while maintaining ease of manufacturing. In addition, the open-loop voltage regulator circuit model ensures precise output voltage by accounting for winding resistance and magnetizing inductance. This article presents an MV SiC gate driver that achieves a partial discharge inception voltage of 11.5 kV and the transformer exhibits a low coupling capacitance of 0.42 pF. Additionally, this article conducts a 6 kV/30 A double pulse test, demonstrating the robust performance of the gate driver even at switching speeds of 133.9 V/ns during turn-off and 111.6 V/ns during turn-on transients.

Gate oscillations exist in paralleled SiC MOSFETs, which can cause false switching behavior and device damage. This article investigates gate oscillations in paralleled 10 kV SiC mosfets as it is currently one of the bottlenecks for paralleling. During the switching transient, the paralleled SiC mosfets operate in their saturation region, where a closed-loop feedback system is formed between the mosfet transconductance and the parasitic distributions in the circuit. The instability of the closed-loop feedback system is key in describing the gate oscillation mechanism. Therefore, a small signal circuit model of two parallel 10 kV SiC mosfets is used to analyze this mechanism, which takes into account both the parasitic inductances and capacitances of the mosfet, power module, and external connections to predict the impact of different parasitic parameters. From the circuit model, four methods are proposed to mitigate the gate oscillations. Finally, experiments are conducted in a double pulse test platform at 6 kV/20 A, showing a good prediction of the gate oscillations and significant damping by the proposed methods.

This article presents an analytical derivation of the volt-second error caused by converter nonlinearities such as dead time and the finite switching speeds of the emerging medium voltage silicon-carbide MOSFETs. The analytical model considers the transient behavior of the MOSFETs, the gate-driving circuitry, and the intrinsic parasitic capacitances of the MOSFETs and the power module. The importance of compensating converter nonlinearities has been revived with the utilization of wide bandgap semiconductor devices as the increased switching frequency penalizes the relative impact of dead time squared in motor drive applications. The first-order analytical model is validated with experimental and simulated results of switching events of a 10 kV silicon-carbide MOSFET power module. In addition, the analytical model is utilized to map out the individual contributions from each time period of the switching event.