In this article, a reliable static random access memory (SRAM) circuit design is proposed for improved thermal and electrical performance at 5-nm technology nodes. The proposed SRAM circuit is developed by incorporating bottom-up approach (from device level to circuit level). The proposed device/circuit design utilizes high thermal conductivity and high permittivity of titanium dioxide (TiO $_{\text{2}}$ ). Specifically, TiO $_{\text{2}}$ -based vertically stacked nanosheet field-effect transistor (NSFET) in the proposed SRAM shows the improvement of maximum lattice temperature ( $\textit{T}_{\text{MAX}}$ ) from 564 to 431 K, which enables the improvement of electron mobility ( $\mu _{\text{electron}}$ ) by 53.1%. In addition, the proposed device structure shows the improvement of ON-current ( $\textit{I}_{\text{on}}$ )/gate current ( $\textit{I}_{\text{gate}}$ ), by 18%/1000%, compared to hafnium oxide (HfO $_{\text{2}}$ )-based vertically stacked NSFET. Because of this thermal/electrical performance boosting, the proposed SRAM circuit shows the enhancement of hold-signal-to-noise margin SNM (HSNM), read-SNM (RSNM), read access time (RAT), and write access time (WAT) at the same time. This thermal and electrical co-improvement indicates that the proposed device structure could enable reliable IC chip design.

This work presents the electro-thermal analysis of crosstalk effects in pristine (undoped) and intercalation doped multilayer graphene nanoribbon interconnects (MLGNRs). A temperature dependent distributed $T-$ network model of MLGNR interconnects has been developed for analyzing the crosstalk induced effects. Further, a temperature-aware gate oxide reliability model has been proposed to compute the crosstalk induced overshoot/undershoot impact on ultra-thin gate oxide for CMOS devices in terms of failure-in-time (FIT) for side-contact (SC) pristine as well as top-contact (TC) Arsenic pentafluoride ( $AsF_{5}$ ), Ferric chloride ( $FeCl_{3}$ ) and Lithium ( $Li$ ) intercalation doped and undoped MLGNR interconnects. Subsequently, comparisons with $Cu$ -based interconnects are made over a range of chip operating temperature from 233K to 450K.