Silicon Carbide (SiC) and Gallium Nitride (GaN) are revolutionizing power electronics with greater efficiency and durability than Silicon. Nevertheless, their widespread use is limited by reliability challenges, including thermal degradation, defect propagation, and charge trapping, affecting their stability and lifetime. This review explores these reliability issues, comparing empirical and physics-based models for predicting device performance and identifying practical limitations. We also examine strategies to enhance robustness, from material design improvements to advanced testing methods. We propose a demonstrative GaN power circuit topology specifically for demonstrating reliability in real-world conditions. This work highlights key challenges and opportunities in developing more reliable SiC and GaN technologies for future applications.

Reliability assessment of semiconductor devices increasingly requires the consideration of multiple degradation mechanisms acting simultaneously over long stress durations. Conventional lifetime qualification and prediction approaches rely on simplified assumptions that can obscure the interpretation of measured degradation data and lead to large uncertainty when extrapolated over many orders of magnitude in time. A consistent analytical framework is therefore required to relate measured degradation behavior to meaningful reliability metrics. This work presents a general framework for semiconductor device reliability that is consistent with established reliability theory and explicitly accommodates multiple competing degradation mechanisms, consistent with modern JEDEC reliability standards. The framework presented here separates physical degradation processes from analytical representations used to interpret experimental data, allowing the effect of independent mechanisms to be combined without imposing an implied physical model. Degradation behaviors exhibiting sublinear time dependence, which are commonly observed across device technologies, are discussed within this context. We show that common data interpretation practices can introduce systematic errors when ssublinearkinetics are present, particularly regarding lifetime extrapolation. A reformulated analytical representation is introduced that improves clarity and robustness in lifetime extraction while remaining fully compatible with standard reliability theory. This framework supports more consistent reliability assessment and more credible lifetime prediction across materials, devices, and operating conditions.

This work examines resistance drift in FPGA I/O paths subjected to combined electrical and thermal stress, using a Xilinx Spartan-6 device as a representative platform. A multiplexed measurement approach was employed, in which multiple I/O pins were externally shorted and sequentially activated, enabling precise tracking of voltage, current, and effective series resistance over time, under controlled bias conditions. Two accelerated stress modes were investigated: high-temperature dwell in the range of 80–120 °C and thermal cycling between 80 and 140 °C. Both stress modes exhibited similar sub-linear (power-law) time dependence on resistance change, indicating cumulative degradation behavior. However, Arrhenius analysis revealed a strong contrast in effective activation energy: approximately 0.62 eV for high-temperature dwell and approximately 1.3 eV for thermal cycling. This divergence indicates that distinct physical mechanisms dominate under each stress regime. The lower activation energy is consistent with electrically and thermally driven on-die degradation within the FPGA I/O macro, including bias-related aging of output drivers and pad-level structures. In contrast, the higher activation energy observed under thermal cycling is characteristic of diffusion- and creep-dominated thermo-mechanical damage in package-level interconnects, such as solder joints. These findings demonstrate that resistance-based monitoring of FPGA I/O paths can discriminate between device-dominated and package-dominated aging mechanisms, providing a practical foundation for reliability assessment and self-monitoring methodologies in complex electronic systems.

Here, we introduce a novel method for the real-time spatial monitoring of I/O interconnection nets in flip-flop packages. Resistance changes in 39 I/O nets are observed simultaneously to produce a spatial profile of the relative degradations of the solder ball joints, interconnection lines, and transistor gates. Location-specific TTF profiles are generated from the degradation data to show the impact of the I/O nets in the context of their placement on the chip. The system succeeds in formulating a clear trend of resistance increase even in relatively mild constant temperature stress conditions. Test results of four temperatures from 80 °C to 120 °C show a dominant degradation pattern strongly influenced by BTI aging demonstrating an acute vulnerability in the pass gates to voltage and temperature stress. The proposed compact spatial monitor solution can be integrated into virtually all chip orientations. The outcome of this study can assist in foreseeing system vulnerabilities in a large spectrum of packaging and advanced packaging orientations in field applications.

Bias temperature instability (BTI) degradation is commonly described using empirical power-law kinetics; however, extraction of the time exponent and projection of lifetime remain highly sensitive to baseline definition and data representation. In conventional approaches, the threshold voltage shift is referenced to an initial value that cannot be measured simultaneously with stress, introducing uncertainty that can produce apparent curvature and variability in the extracted exponent. In this work, a baseline-independent linearization method is applied to representative published datasets spanning advanced silicon, SiC MOSFETs, and GaN power devices. By analyzing the measured degradation trajectories directly in a transformed time coordinate, the method removes curvature associated with baseline ambiguity and enables consistent extraction of the effective power-law exponent. Across all material systems examined, the extracted exponent exhibits systematic dependence on applied stress once baseline effects are reduced. This behavior challenges the commonly assumed constant-exponent formulation used in conventional lifetime projections and shows that even modest variations in the exponent can produce large differences in projected time-to-failure. A transformed lifetime representation based on ${\mathrm{T}\mathrm{T}\mathrm{F}}^n$ is introduced, in which the influence of exponent variation is separated from the intrinsic voltage and temperature acceleration of the degradation rate. In this representation, the extracted acceleration parameters become more stable and physically interpretable. This formulation is consistent with standard reliability frameworks, including JEDEC JEP122G, in which the time exponent enters directly into the lifetime expression. These results demonstrate that baseline-independent analysis provides a unified framework for interpreting BTI degradation across disparate semiconductor technologies and suggest that explicit treatment of stress-dependent exponents is required for physically consistent lifetime modeling.

The long-term electrical stability of GaN high-electron-mobility transistors (HEMTs) is strongly influenced by charge trapping under electrical stress, which can affect threshold voltage (V_TH), on-resistance (R_DS), and gate leakage current (I_GS). In this work, the temporal evolution of these parameters is systematically investigated in depletion-mode GaN-on-SiC HEMTs subjected to prolonged sequential electrical stress. Three nominally identical devices from the same wafer were exposed to the same stress sequence, including negative gate biases from −5 to −9 V, positive gate-bias recovery, repeated negative gate stress, and drain-current stress up to 0.5 A under controlled temperature conditions. I_GS was monitored continuously during stress, whereas V_TH and R_DS were periodically extracted using brief measurement interruptions. The study focuses on cumulative long-term parameter evolution rather than switching-cycle or fast dynamic R_DS(on) behavior. Within the sequential negative-bias protocol, the −5 to −7 V stress segments exhibited stronger time-dependent evolution of V_TH and R_DS, whereas the subsequent −8 and −9 V segments showed reduced incremental drift. Because these conditions were applied sequentially, this behavior reflects the combined influence of gate-bias magnitude and accumulated stress history rather than an isolated voltage-acceleration relationship. Positive gate bias produced partial recovery of V_TH and R_DS, indicating a reversible component of the electrically induced parameter shift. Reapplication of −5 V stress after the recovery phase resulted in altered degradation kinetics, demonstrating a pronounced dependence on prior stress history. Drain-current stress at zero gate bias produced comparatively limited long-term parameter drift within the investigated range, whereas combined positive gate bias and drain current increased electrical instability. These results demonstrate that the electrical state established by previous stress conditions strongly influences subsequent GaN HEMT behavior. Although the present measurements do not uniquely identify trap energies or spatial locations, they provide a reproducible experimental basis for evaluating history-dependent trapping and long-term parameter stability in GaN power devices.