High-electron mobility transistors (HEMTs) based on ultrathin AIN/GaN heterostructures with a 3.5-nm AlN barrier and a 3-nm Al₂O₃ gate dielectric have been investigated. Owing to the optimized AIN/GaN interface, very high carrier mobility (~1400 cm²/V ldr s) and high 2-D electron-gas density (~2.7times10¹³/cm²) resulted in a record low sheet resistance (~165 Omega/sq). The resultant HEMTs showed a maximum dc output current density of ~2.3 A/mm and a peak extrinsic transconductance g_m,ext~480 mS/mm (corresponding to g_m,int~1 S/mm). An f_T/f_max of 52/60 GHz was measured on 0.25times60 mum² gate HEMTs. With further improvements of the ohmic contacts, the gate dielectric, and the lowering of the buffer leakage, the presented results suggest that, by using AIN/GaN heterojunctions, it may be possible to push the performance of nitride HEMTs to current, power, and speed levels that are currently unachievable in AlGaN/GaN technology.

The large electronic polarization in III-V nitrides allows for novel physics not possible in other semiconductor families. In this work, interband Zener tunneling in wide-band-gap GaN heterojunctions is demonstrated by using polarization-induced electric fields. The resulting tunnel diodes are more conductive under reverse bias, which has applications for zero-bias rectification and mm-wave imaging. Since interband tunneling is traditionally prohibitive in wide-band-gap semiconductors, these polarization-induced structures and their variants can enable a number of devices such as multijunction solar cells that can operate under elevated temperatures and high fields.

We report gallium arsenide (GaAs) growth rates exceeding 300 µm h⁻¹ using dynamic hydride vapor phase epitaxy. We achieved these rates by maximizing the gallium to gallium monochloride conversion efficiency, and by utilizing a mass-transport-limited growth regime with fast kinetics. We also demonstrate gallium indium phosphide growth at rates exceeding 200 µm h⁻¹ using similar growth conditions. We grew GaAs solar cell devices by incorporating the high growth rate of GaAs and evaluated its material quality at these high rates. Solar cell growth rates ranged from 35 to 309 µm h⁻¹ with open circuit voltages ranging from 1.04 to 1.07 V. The best devices exceeded 25% efficiency under the AM1.5 G solar spectrum. The high open-circuit voltages indicate that high material quality can be maintained at these extremely high growth rates. These results have strong implications toward lowering the deposition cost of III-V materials potentially enabling the deposition of high efficiency devices in mere seconds.

The importance of exfoliation techniques increases as the semiconductor industry progresses toward thinner devices as a way to reduce material costs and improve performance. The controlled spalling technique is a recently developed substrate removal process that utilizes the physics of fracture to create wafer cleavage parallel to the surface at a precise depth. In this letter, we apply principles of linear elastic fracture mechanics to predict the process conditions needed to exfoliate (100) GaAs of a desired thickness. Spalling can be initiated in a controllable manner, by depositing a stressor film of a residual stress value just below the threshold value to induce a spontaneous spall. Experimental data show process window requirements to controllably spall (100) GaAs. Additionally, experimental spall depth in (100) GaAs compares well to spalling mechanics predictions when the effects of wafer thickness and modulus are considered. To test spalled material quality, III-V single junction photovoltaic devices are lifted off of a (100)-GaAs substrate by spalling methods and electrical characteristics are recorded. No degradation is observed in the spalled device, illustrating the potential of this method to rapidly produce thin, high quality devices.