Counting has become a fundamental task for data processing in areas such as microbiology, medicine, agriculture and astrophysics. The proposed SA-CNN-DC (Scale Adaptive—Convolutional Neural Network—Distance Clustering) methodology in this paper is designed for automated counting of steel bars from images. Its design consists of two Machine Learning techniques: Neural Networks and Clustering. The system has been trained to count round and squared steel bars, obtaining an average detection accuracy of 98.81% and 98.57%, respectively. In the steel industry, counting steel bars is a time consuming task which highly relies on human labour and is prone to errors. Reduction of counting time and resources, safety and productivity of employees and high confidence of the inventory are some of the advantages of the proposed methodology in a steel warehouse.

A low-temperature coefficient, curvature-compensated CMOS bandgap voltage reference (BGR) is presented in this paper. The design was implemented in standard 0.18μm CMOS process with 1.8V power supply. The compensation is achieved generating the negative temperature coefficient (TC) voltage with a quadratic temperature dependent current biasing a bipolar transistor. In addition, the design has a 4-bit trimming circuit to compensate for process variations. The output voltage is 1.225V and shows a TC lower than 2ppm/°C over a temperature range of 160°C (-20°C to 140°C). The bandgap reference consumes 620μW and its total layout area is 217×147μm ² .

For current microelectronic integrated systems, the design methodology involves different steps that end up in the full system simulation by means of electrical and physical models prior to its manufacture. However, the higher the circuit complexity, the more time is required to complete these simulations, jeopardizing the convergence of the numerical methods and, hence, meaning that the reliability of the results are not guaranteed. This paper shows the use of a high-level tool based on Matlab to simulate the operation of an artificial neural network implemented in a mixed analog-digital CMOS process, intended for sensor calibration purposes. The proposed standard tool enables modification of the neural model architecture to adapt its characteristics to those of the electronic system, resulting in accurate behavioral models that predict the complete microelectronic IC system behavior under different operation conditions before its physical implementation with a simple, time-efficient, and reliable solution.

An integrated machine-learning based adaptive circuit for sensor calibration implemented in standard $0.18~\mu \text{m}$ CMOS technology with 1.8V power supply is presented in this paper. In addition to linearizing the device response, the proposed system is also capable to correct offset and gain errors. The building blocks conforming the adaptive system are designed and experimentally characterized to generate numerical high-level models which are used to verify the proper performance of each analog block within a defined multilayer perceptron architecture. The network weights, obtained from the learning phase, are stored in a microcontroller EEPROM memory, and then loaded into each of the registers of the proposed integrated prototype. In order to verify the proposed system performance, the non-linear characteristic of a thermistor is compensated as an application example, achieving a relative error $e_{r}$ below 3% within an input span of $130^\circ C$ , which is almost 6 times less than the uncorrected response. The power consumption of the whole system is 1.4mW and it has an active area of 0.86mm 2 . The digital programmability of the network weights provides flexibility when a sensor change is required.

A CMOS digitally programmable analogue processor used in a neural network to linearize an NTC thermistor is presented in this paper. Particularly, the work focuses on the multiplier block and presents an alternative way to increase the weight resolution without oversizing the system. A neural network designed for linearization of the NTC thermistor is tested. Two architectures (the 8-bit and the proposed 8 1/2-bit multiplier) are compared and the neural network is simulated by means of mathematical models in order to compare performance.