In this brief, several issues attributed to the channel-release process in vertically stacked-gate-all-around MOSFETs (GAAFETs) having various nanosheet (NS) widths were rigorously investigated. Because of the finite selectivity of SiGe (sacrificial layer) etchant to Si (channel layer), Si channel is likely to be thinned during the channel-release step which is one of the key processes in stacked-GAA FET fabrication. Consequently, the thickness of channel and the interchannel space becomes variable depending on the NS width, since the etch time must be determined by the widest channel within a wafer. It results in a channel width dependence of gate work function, gate-to-drain capacitance, and channel interfacial property as well as the electrostatic gate controllability. The electrical characteristic behavior of stacked-GAAFETs induced by these effects was thoroughly investigated through process-based 3-D technology computer-aided design (TCAD) device simulation along with a transmission electron microscopy (TEM) and an energy-dispersive spectroscopy (EDS) analyses. The results confirm that width-dependent effects should be taken into account when fabricating and compact modeling the stacked-GAAFETs with various NS widths which are required for logic and static random access memory (SRAM) applications.

In this article, a 5-nm node two-stack nanosheet FET with a triple-k spacer structure representing three spacer regions consisting of two inner spacers (inner spacer 1 and inner spacer 2) formed by two atomic layer deposition (ALD) processes leveraging the inner spacer formation-process method and outer spacer process of stack gate-all-around (GAA) process is proposed. Material and structure optimization was performed to confirm the effects of each spacer regions. Inner spacer 1 has a direct effect on the channel extension region. However, the inner spacer 2 is not in direct contact with the channel extension region and the gate, thus confirming the relatively indirect effect. In addition, the material dependence of the outer spacer, formed between the gate and the side region of the channel where the field is concentrated, was confirmed. By comparing the optimized triple-k spacer structure with the fully nitride spacer, the improved dynamic performance, as well as the active power and static power, was identified.

In this article, structure optimization of high-k interfacial layer (IL), deposited between the gate and the gate sidewall spacer, was performed in a 5-nm node nanosheet field-effect transistor (NSFET). High-k IL can be formed during the high-k gate dielectric and metal gate (HKMG) with gate-last process. By optimizing the structure of thickness of high-k IL (Thk) with gate length (LG), spacer length (Lext), and source/drain (S/D) length (LS/D), improved electrical performances were obtained. By optimizing Thk with properly adjusted LG, Lext, and LS/D, highly saturated on-/off-current ratio (Ion/Ioff) was obtained with appropriate drain-induced barrier lowering (DIBL). Besides, reduced intrinsic gate delay (Cgg) properties and off-state leakage current were identified. In addition, the reason of increased off-state leakage, which can be shown when Lext shrinks with extending Thk, was also investigated. Finally, the optimized electrical characteristics were obtained when Thk is adjusted with LG and LS/D. The power was reduced about 27% with the same performance and 18% enhanced performance was obtained when Thk is optimized through LG. On the contrary, reduced off-state leakage current and DIBL were confirmed in the case of optimization point with LS/D, which result in lower static power. Based on this comparison, optimization method and guideline for high-k IL was proposed.

In this paper, the structural and material optimization of gate sidewall spacer in the perspective of off-state leakage current was performed in a 3-nm node nanoplate FET (NPFET). Gate-induced drain leakage (GIDL) current, a dominant factor of off-state leakage current, and active performance (on-current, on/off current ratio, and dynamic performance) were co-optimized according to the structural correlation of gate sidewall spacer with other structural components such as gate, source, and drain length. By optimizing the structure for gate and spacer, intrinsic delay was improved by 9.8%, GIDL current was reduced by ~ 78%, and then on/off current ratio (Ion/Ioff) was enhanced by 4.2 times. On-current (Ion) according to contact resistance (Rcon) and dynamic performance was analyzed in relation to source/drain (S/D) and spacer. Consequently, the intrinsic delay was improved by 10% and GIDL current reduced by about 92%, which enhanced Ion/Ioff by 7.9 times accordingly. Furthermore, by comparing structural relations between gate spacer and S/D spacer, a better structural optimization method was proposed.

L-shaped tunnel field-effect transistor (TFET) provides higher on-current than a conventional TFET through band-to-band tunneling in the vertical direction of the channel. However, L-shaped TFET is disadvantageous for low-power applications because of increased off-current due to the large ambipolar current. In this paper, a stacked gate L-shaped TFET is proposed for suppression of ambipolar current. Stacked gates can be easily implemented using the structural features of L-shaped TFET, and on- and off-current can be controlled separately by using different gates located near the source and the drain, respectively. As a result, the suppression of ambipolarity is observed with respect to work function difference between two gates by simulation of the band-to-band tunneling generation. Furthermore, the proposed device suppresses ambipolar current better than existing ambipolar current suppression methods. In particular, low drain resistance is achieved as there is no need to reduce drain doping, which leads to a 7% enhanced on-current. Finally, we present the fabrication method for a stacked gate L-shaped TFET.