This article provides a review of semiconductor based ionising radiation sensors to measure accumulated dose and detect individual strikes of ionising particles. The measurement of ionising radiation ($\gamma$-ray, X-ray, high energy UV-ray and heavy ions, etc.) is essential in several critical reliability applications such as medical, aviation, space missions and high energy physics experiments considering safety and quality assurance. In the last few decades, numerous techniques based on semiconductor devices such as diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs) and solid-state photomultipliers (SSPMs), etc., have been reported to estimate the absorbed dose of radiation with sensitivity varying by several orders of magnitude from $\mathsf{\mu }$Gy to MGy. In addition, the mitigation of soft errors in integrated circuits essentially requires detection of charged particle induced transients and digital bit-flips in storage elements. Depending on the particle energies, flux and the application requirements, several sensing solutions such as diodes, static random access memory (SRAM) and NAND flash, etc., are reported in the literature. This article goes through the evolution of radiation dosimeters and particle detectors implemented using semiconductor technologies and summarises the features with emphasis on their underlying principles and applications. In addition, this article performs a comparison of the different methodologies while mentioning their advantages and limitations.

An energy-efficient and supply- and temperature-resilient resistive sensor interface in 130-nm CMOS technology is presented. Traditionally resistive sensors are interfaced with a Wheatstone bridge and an amplitude-based analog-to-digital converter (ADC). However, both the unbalanced Wheatstone bridge and the ADC are highly affected by supply voltage variations, especially in smaller CMOS technologies with low supply voltages. As alternative to ratiometric measuring, this paper presents a force-balanced Wheatstone bridge interface circuit with a highly digital architecture that combines the advantage of energy-efficient sensing with highly improved overall PSRR and temperature resilience in one circuit. The prototyped circuit has a noise-frequency-independent PSRR of 52 dB, even for supply-noise amplitudes up to +10 dB FS. The maximum absolute output error in a supply voltage range of 0.85-1.15 V is only 0.7%, while the maximum absolute output error in a temperature range of 100°C is only 0.56% or 56 ppm/°C. The complete interface is prototyped in 130-nm CMOS and consumes 124.5 μW from a 1-V supply with a 10-kHz input bandwidth and 10.4-b resolution and 8.9-b linearity, resulting in a state-of-the-art sensor figure of merit of 13.03 pJ/bit-conversion.

In this article, a hybrid step-up/down converter is presented with improved efficiency, smaller form factor, and enhanced reliability for Li-ion-battery-operated power management integrated circuits. Utilizing a hybrid structure with one inductor and two flying capacitors, the dual-path buck–boost (DPBB) converter reduces the average inductor current, switch currents, and the required blocking voltage for the power switches. To support a mid-3-V output from a Li-ion battery, the converter can be realized using 1.8-V rated devices, solely. In addition, the DPBB facilitates a continuous input and output current delivery, thus improving the reliability of the converter significantly. Besides, leveraging the Li-ion battery charge profile, the topology provides an optimal performance during downconversion, in which the converter operates for most of its usage time. With reduced inductor current and smaller voltage rated switches, a more compact inductor with a large dc resistance (DCR) can be used to maintain similar efficiency, which, in turn, helps reduce the converter board space and associated manufacturing cost. Fabricated in a 180-nm BCD technology, the prototype achieves a peak efficiency of 95.63% even for a large 288-m $\Omega$ inductor DCR with an output ripple below 20 mV for a load current up to 700 mA.

Radiation and extreme temperature are the main inhibitors for the use of electronic devices in space applications. Radiation challenges the normal and stable operation of DC-DC converters, used as power supply for onboard systems in satellites and spacecrafts. In this situation, special design techniques known as radiation hardening or radiation tolerant designs have to be employed. In this work, a module level design approach for radiation hardening is addressed. A module in this sense is a constituent of a digital controller, which includes an analog to digital converter (ADC), a digital proportional-integral-derivative (PID) controller, and a digital pulse width modulator (DPWM). As a new Radiation Hardening by Design technique (RHBD), a four module redundancy technique is proposed and applied to the digital voltage mode controller driving a synchronous buck converter, which has been implemented as hardware-in-the-loop (HIL) simulation block in MATLAB/Simulink using Xilinx system generator based on the Zynq-7000 development board (ZYBO). The technique is compared, for reliability and hardware resources requirement, with triple modular redundancy (TMR), five modular redundancy (FMR) and the modified triplex–duplex architecture. Furthermore, radiation induced failures are emulated by switching all duplicated modules inputs to different signals, or to ground during simulation. The simulation results show that the proposed technique has 25% and 30%longer expected life compared to TMR and FMR techniques, respectively, and has the lowest hardware resource requirement compared to FMR and the modified triplex–duplex techniques.

This paper presents a novel radiation monitor which is based on a custom SRAM (Static Random Access Memory) ASIC. Its sensitivity is adjustable through its core supply voltage and the radiation monitoring is based on the upset rate that is measured during a measurement-interval in the memory. The sensor has different supply voltages for the SRAM core and the interface logic to prevent incorrect digital signals during the measurement cycle. The memory was processed in a 0.18 μm CMOS technology and was tested with heavy ions with an LET from 1.8 - 60 MeV.cm2/mg, 24 GeV protons and a mixed radiation field. The memory cells were also verified with a Two- Photon Absorption (TPA) Laser. Furthermore, an analysis was made on Single-Event Upsets and multi-bit upsets.