This article provides a review of semiconductor based ionising radiation sensors to measure accumulated dose and detect individual strikes of ionising particles. The measurement of ionising radiation ($\gamma$-ray, X-ray, high energy UV-ray and heavy ions, etc.) is essential in several critical reliability applications such as medical, aviation, space missions and high energy physics experiments considering safety and quality assurance. In the last few decades, numerous techniques based on semiconductor devices such as diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs) and solid-state photomultipliers (SSPMs), etc., have been reported to estimate the absorbed dose of radiation with sensitivity varying by several orders of magnitude from $\mathsf{\mu }$Gy to MGy. In addition, the mitigation of soft errors in integrated circuits essentially requires detection of charged particle induced transients and digital bit-flips in storage elements. Depending on the particle energies, flux and the application requirements, several sensing solutions such as diodes, static random access memory (SRAM) and NAND flash, etc., are reported in the literature. This article goes through the evolution of radiation dosimeters and particle detectors implemented using semiconductor technologies and summarises the features with emphasis on their underlying principles and applications. In addition, this article performs a comparison of the different methodologies while mentioning their advantages and limitations.

In this work, a comparison has been made between a low noise ring-oscillator and an LC-oscillator Phase Locked Loop (PLL). An ASIC has been developed to conduct irradiation experiments targeting high-energy physics applications. Two different samples were irradiated up to a total ionizing dose (TID) in SiO2 of 200 Mrad and 600 Mrad with a 100C thermal annealing step. Single-Event Upset (SEU) tests were performed with heavy ions with LETs (Linear Energy Transfer) between 3.2 and 69.2 MeV.cm2/mg. A Two-photon absorption (TPA) laser facility has been used to provide detailed results on the SEU sensitivity. Both independent PLLs have identical loop dynamics to allow a fair comparison including a Triple-Modular Redundant (TMR) divider and TMR phase detector. Furthermore these circuits consume the same amount of power. The PLLs were processed in a commercial 65 nm CMOS technology.

This paper presents a radiation tolerant Phase-Locked Loop (PLL) CMOS ASIC with an optimized Voltage Controlled Oscillator (VCO) for Single-Event Upsets (SEUs). The circuit is designed for high-energy particle physics experiments for low-jitter clock generation and clock recovery. An optimal tuning strategy of the VCO is presented that minimizes the cross-section and the SEU sensitivity of the oscillator. The circuit is processed in a 65 nm CMOS technology and has been irradiated with heavy ions with an LET (Linear Energy Transfer) between 10 to 69.2 MeV.cm²/mg. A comparison has been made with a conventional oscillator which proves a significant improvement in SEU sensitivity.

Commissioning of detector systems for the High-Luminosity Large Hadron Collider (HL-LHC) is scheduled to take place between 2026 and 2028 at CERN. Application Specific Integrated Circuits (ASICs) for those systems have been in intense development over the past ten years. Some of those ASICs, as is the case of the Low Power GigaBit Transceiver (lpGBT) described in this work, have now been produced in industrial quantities and have been fully qualified for operation in the HL-LHC environments that require, where the innermost detectors are concerned, radiation hardness in excess of 1 MGy. The lpGBT is a multi-functional device, enabling data transmission between the off-detector and the on-detector systems. Data can be transmitted from the detector at 5.12 Gbit s ⁻¹ and 10.24 Gbit s ⁻¹ and to the detector at 2.56 Gbit s ⁻¹ . It implements data rate-configurable electrical links to communicate with the front-end ASICs and low-speed serial and parallel buses for experiment control. A set of analog functions for monitoring and control of the physics detectors is also included. This paper describes the functionality and the architecture of the lpGBT ASIC and reports on its radiation hardness characterization.

This article presents a static random access memory (SRAM)-based flexible radiation monitor. The monitor was fabricated in a 65-nm CMOS technology and it is designed as an application-specific integrated circuit, which comprises 768k bits SRAM cell matrix with individual power supply and a digital control core with a serial peripheral interface (SPI). By adjusting the core voltage of the SRAM matrix, the radiation sensitivity was made flexible. Also, SRAM cells with different threshold voltages were implemented to get further extension on tunable sensitivity range. The monitor has been tested under heavy ions with a linear energy transfer (LET) from 1.5 to 48.5 MeV·cm ² /mg, high-energy (50-186 MeV) and low-energy (0.7-5 MeV) protons, and 14-MeV and thermal neutrons. An analysis was performed on how single-event upset sensitivity changes while tuning the supply voltage under different radiation environments. The results show that the monitor has the potential for space and facility applications.

This paper presents a Single Event Upset (SEU) robust low phase-noise PLL for clock generation in harsh environments like nuclear and space applications. The PLL has been implemented in a 65 nm CMOS technology. A low noise LC-tank oscillator is included with a tuning range from 2.2 GHz to 3.2 GHz. The PLL includes a new phase detector and divider with Triple Modular Redundancy (TMR) to suppress Single Event Effects in ionizing radiation environments. A highly reconfigurable bandwidth from 0.7 MHz to 2 MHz provides optimal reference phase noise filtering. The PLL has been designed and measured to operate in a temperature range from -25 C to 125 C and features a jitter of 345 fs rms with a power consumption of 11.7 mW and is tolerant to 10 % supply variations. Single Event Upset laser tests are performed to verify the triplicated circuit performance.