An extremely low-power 32-kHz crystal oscillator (XO) based on a sub-harmonic pulse injection technique is presented. By injecting current pulses into the crystal at the sub-harmonic of the oscillation frequency, the power consumption of the proposed XO reduces with an increase in the order of sub-harmonic (N). For the generation of sub-harmonic pulses with accurate timing, a 50%-duty-cycle-locked loop and a sub-harmonic peak-detection delay-locked loop are employed. A clock divider is also utilized to generate the sub-harmonic clock, which is required for the real-time clock as well. Implemented in a 55-nm CMOS technology with a triple well, the proposed XO, including a clock divider, dissipates 0.74 nW from a single 0.3-V supply for N = 16 and the chip occupies only 0.019 mm².

In this article, we propose a nested feedforward noise canceling (NFF-NC) technique for transimpedance amplifier (TIA) in optical link communication. The proposed technique minimizes the noise voltages due to both the first and second stages of the TIA, which provides substantial improvement in its noise performance over conventional noise canceling (NC) topology. Comprehensive analysis and comparison are performed between two techniques. While not degrading other key performance parameters (e.g., bandwidth, gain, and power consumption), our proposed scheme presents 30% noise reduction compared to conventional scheme. The proposed NC architecture provides the improved stability since NFF-NC scheme inherently presents an additional left half-plane (LHP) zero due to the FF-stage. The loop stability performance is verified over several process corners, temperatures, and voltage variations confirming the detailed analysis in its loop gain and loop parameters. The proposed NFF-NC TIA was implemented in a 65-nm CMOS technology. The implemented TIA consumes 10.1 mW of power from a 1.3-V supply and occupies 0.037 mm ² of core area. The measurement results show that the proposed TIA presents dc transimpedance gain of 56.3 dB $\Omega $ and bandwidth (−3 dB) of 6.5 GHz. An average input-referred noise current density, $\overline {i_{n,\text {in},\text {avg}}}$ , is 15.1 pA/(Hz) ^1/2 over the bandwidth. Eye diagram is also measured with a pseudorandom binary sequence (PRBS) of 2 ⁷ – 1 with the data rate at 8.5 Gb/s.

This article presents an interference-resilient high-sensitivity binary frequency-shift keying (BFSK) multi-channel wake-up receiver (WuRX) supporting 900-MHz bands for low-power wide-area network (LPWAN) applications. The proposed WuRX uses a direct-conversion architecture, a frequency-to-energy demodulator, and a 4096-bit correlator. Direct conversion using a 50%-to-25% duty-cycle conversion mixer and two-stage ring voltage-controlled oscillator (VCO) minimizes the power consumption. The frequency-to-energy demodulator offers a process-voltage-temperature (PVT) variation-tolerant symbol recovery based on an image rejection $n$ -path filter (IRNF), a poly-phase filter (PPF), and a quadrature envelope detector (ED). The 4096-bit correlator provides a digital processing gain of about 17 dB, improving both the sensitivity and the selectivity. To reduce the power consumption further, the proposed WuRX supports an asynchronous duty-cycling operation based on repetition of the wake-up code. Implemented in the 55-nm complementary metal–oxide–semiconductor (CMOS), the proposed WuRX achieves sensitivity of −124 dBm in the always-on mode while dissipating 781 $\mu \text{W}$ . For the duty-cycling mode with wake-up codes repeated 15 times, the proposed WuRX exhibits the same sensitivity of −124 dBm with reduced power consumption of 114 $\mu \text{W}$ and extended wake-up latency of 1.966 s. The proposed WuRX shows robust interference resilience with a signal-to-interference ratio (SIR) of −76 dB at a 20-MHz offset against a continuous wave (CW). The CMOS radio module, including the proposed WuRX, showed packet-error rates (PERs) of 0% and 5.7% in the 4.8- and 9.8-km ground-to-ground wireless communication tests, respectively.

A broadband receiver front-end with low noise figure and flat conversion gain response is presented in this paper. The receiver front-end is a part of the broadband spectrum sensing receiver and processes 30–40 GHz of broad input spectrum followed by down-conversion to DC-10 GHz of IF signal. The proposed work is comprised of a low noise amplifier (LNA), on-chip passive Balun, down conversion mixer, and output buffer. To achieve front-end target specification over 10 GHz input bandwidth, the stagger-tuned LNA is employed and the down conversion mixer is loaded with a 3rd-order LC ladder low pass filter. The prototype chip was implemented in 45 nm CMOS technology. The chip achieves 10.3–16.5 dB conversion gain, 5.9 dB integrated NF, and −11 dBm IIP3 from 30 to 40 GHz. The chip is realized within 0.42 mm ${}^2$ and consumes 96 mW from a 1.2 V supply.

This brief presents the CMOS fractional-N frequency synthesizer for UHF RFID reader applications. With stringent phase noise (PN) specifications for UHF RFID transceiver, our proposed synthesizer is designed to have a narrow loop bandwidth and $2^{nd}$ -order loop filter as the optimum solution paired with low noise VCO. Then, we propose the transformer-based impulse sensitivity function (ISF) manipulating VCO that supports the target PN of the frequency synthesizer, albeit with large pass-band characteristic. Compared to conventional ISF manipulating VCO, our proposed solution improves the PN by 11.3 and 14.7 dB at 10 kHz and 1 MHz offset frequencies, respectively. Figure of merit (FOM) is also superior to conventional one by 7.4 and 10.9 dB at aforementioned offset frequencies. The frequency synthesizer is implemented in a 55nm CMOS technology as a part of the UHF RFID transmitter and consumes 38.4 mW power with 0.413 $mm^{2}$ active area. With comparison to the state-of-the-art frequency synthesizer at sub-6GHz operating frequency, only our solution satisfies the target PN for EPC global standard and various local regulations across the entire UHF RFID operating frequency range.