The analysis of quantum mechanical confinement in recent germanium electron–hole bilayer tunnel field-effect transistors has been shown to substantially affect the band-to-band tunneling (BTBT) mechanism between electron and hole inversion layers that constitutes the operating principle of these devices. The vertical electric field that appears across the intrinsic semiconductor to give rise to the bilayer configuration makes the formerly continuous conduction and valence bands become a discrete set of energy subbands, therefore increasing the effective bandgap close to the gates and reducing the BTBT probabilities. In this letter, we present a simulation approach that shows how the inclusion of quantum confinement and the subsequent modification of the band profile results in the appearance of lateral tunneling to the underlap regions that greatly degrades the subthreshold swing of these devices. To overcome this drawback imposed by confinement, we propose an heterogate configuration that proves to suppress this parasitic tunneling and enhances the device performance.

Electron–Hole Bilayer Tunneling Field-Effect Transistors are typically based on band-to-band tunneling processes between two layers of opposite charge carriers where tunneling directions and gate-induced electric fields are mostly aligned (so-called line tunneling). However, the presence of intense electric fields associated with the band bending required to trigger interband tunneling, along with strong confinement effects, has made these types of devices to be regarded as theoretically appealing but technologically impracticable. In this work, we propose an InAs/GaSb heterostructure configuration that, although challenging in terms of process flow design and fabrication, could be envisaged for alleviating the electric fields inside the channel, whereas, at the same time, making quantum confinement become the mechanism that closes the broken gap allowing the device to switch between OFF and ON states. The utilization of induced doping prevents the harmful effect of band tails on the device performance. Simulation results lead to extremely steep slope characteristics endorsing its potential interest for ultralow power applications.

The inclusion of quantum effects in the transport direction plays an important role in the extensive research of ultrascaled electronic devices. In this context, it is necessary to study how these phenomena affect different technological architectures in order to conclude which one can be the best candidate to replace standard technology. This paper presents the implementation of direct source-to-drain tunneling effect in a multisubband ensemble Monte Carlo simulator showing its influence in different structures such as fully depleted silicon-on-insulator, double-gate silicon-on-insulator, and FinFET devices. The differences in the potential profile and the electron distribution in the subbands for these architectures modify the number of electrons affected by this quantum mechanism and, therefore, their short-channel behavior.

We propose and validate a novel design methodology for logic circuits that exploits the conduction mechanism and the presence of two independently biased gates (“n-gate” and “p-gate”) of the electron-hole bilayer tunnel field-effect transistor (EHBTFET). If the device is designed to conduct only under certain conditions, e.g., when V _n-gate = V _DD and V _p-gate = 0, it then shows an “XOR-like” behavior that allows the implementation of certain logic gates with a smaller number of transistors compared to conventional CMOS static logic. This simplifies the design and possibly results in faster operation due to lower node capacitances. We demonstrate the feasibility of the proposed EHBTFET logic for low supply voltage operation using mixed device/circuit simulations including quantum corrections.

Leakage phenomena are increasingly affecting the performance of nanoelectronic devices, and therefore, advanced device simulators need to include them in an appropriate way. This paper presents the modeling and implementation of direct source-to-drain tunneling (S/D tunneling), gate leakage mechanisms (GLMs) accounting for both direct tunneling and trap-assisted tunneling, and nonlocal band-to-band tunneling (BTBT) phenomena in a multissubband ensemble Monte Carlo (MS-EMC) simulator along with their simultaneous application for the study of ultrascaled fully depleted silicon-on-insulator, double-gate silicon-on-insulator, and FinFET devices. We find that S/D tunneling is the prevalent phenomena for the three devices, and it is increasingly relevant for short-channel lengths.