This paper presents an analog front-end (AFE) specially developed for a water conductivity measurement system for water network management applications. Water conductivity is one of the best ways to detect a problem with the water in the network. In order to trigger an alarm it is only required to detect a 10 % variation, which allows to simplify the system design. The proposed sensor uses four platinum micro-machined electrodes, where a 6 kHz signal is applied to the outer electrodes and a voltage signal is read in the inner ones. A programmable switched-capacitor (SC) bandpass filter is included in the analog-to-digital (A/D) channel to attenuate the interference from the 50 Hz power network, that shares the same environment with the water network, and to allow using a square wave signal to drive the sensor, thus simplifying the overall system. The resulting sine wave is digitized using a passive continuous-time (CT) 2nd order Σ modulator. The output bitstream is decimated, using a sinc filter, and the RMS value of the voltage is calculated. The A/D acquisition channel was implemented in a 130 nm CMOS technology, using a supply voltage of 0.9 V and a clock frequency of 1 MHz (SC amplifier and SC bandpass filter) and 4 MHz (Σ modulator). Measurement results show a SNDR of 44.4 dB for an input signal of 6 kHz and an amplitude of -41 dBV. The channel dissipates 386 μW and occupies an area of 0.27 mm.

This brief presents a programmable second-order bandpass switched-capacitor filter implemented for an Internet-of-Things water management sensor node. The filter circuit, which is based on the Sallen-Key topology, is implemented using a low-gain amplifier (<;2), avoiding designing high-gain high bandwidth opamps, which can be difficult to design in advanced CMOS technologies, due to the reduction of the supply voltage and of the intrinsic gain of the transistors. Without the high gain, the circuit becomes sensitive to the effects of parasitic capacitances, which have to be minimized and compensated during the design process. The filter circuit was designed and fabricated in a 130-nm CMOS technology, using a supply voltage of only 0.9 V, to reduce the power dissipation, and a clock frequency of 1 MHz. Measurement results show that the filter's central frequency can be tuned between 3.9 kHz and 7.1 kHz, the gain between -6.4 dB and 12.6 dB, and the quality factor between 0.9 and 6.9. In the default digital control code of the capacitor banks, the circuit has an IM3 of -66.5 dB. The total power consumption is 257 μW.

This paper presents an efficient numerical methodology to obtain the frequency response of switched-capacitor filters based on the circuits' differential equations. This methodology uses a non-hierarchical approach in which the non-ideal effects of the transistors (in the switches and in the amplifier) are taken into consideration, allowing the accurate computation of the frequency response, even in the case of incomplete settling in the SC branches. The accuracy is demonstrated by comparing the results obtained using the proposed methodology with those obtained using transient electrical simulation results for three different SC circuits: a first order SC passive filter, a second order SC lowpass filter, and a second order SC bandpass filter, showing that the results are in good agreement with the more time consuming electrical simulation of the circuits.

This paper presents a SC biquad using a simple quasi-unity gain amplifier. In sub-nanometer CMOS technologies the intrinsic gain of the transistors is low, this increases the difficulty of designing high gain amplifiers. The proposed SC filter is based on the Sallen-Key biquad and it requires only a simple low gain amplifier. A differential filter circuit, including a suitable low gain amplifier based on a fully-differential voltage-combiner is presented. The correct functionality of this circuit is validated through electrical simulations of a cascaded sixth order filter. These simulations show that for a clock frequency of 100 MHz, the frequency response of the circuit is very similar to the one of the prototype filter, with only a relative error of 1.1% in the attenuation value at the cutoff frequency.

An energy harvesting system can use a supercapacitor in order to store energy; however, a voltage regulator is required to obtain a constant output voltage as the supercapacitor discharges. A Switched-Capacitor DC-DC converter allows for complete integration in CMOS technology, but requires several topologies in order to obtain a high efficiency. This paper presents the complete analysis of these topologies in order to determine expressions that allow to design and determine the optimum input voltage ranges for each topology. These expressions are verified using electrical simulations.