Gallium nitride (GaN)-based vertical power Schottky barrier diode (SBD) has demonstrated outstanding features in high-frequency and high-power applications. This paper reviews recent progress on GaN-based vertical power SBDs, including the following sections. First, the benchmark for GaN vertical SBDs with different substrates (Si, sapphire, and GaN) are presented. Then, the latest progress in the edge terminal techniques are discussed. Finally, a typical fabrication flow of vertical GaN SBDs is also illustrated briefly.

Recent research has revealed that SiC power MOSFETs can experience failures at remarkably low gate stress after heavy ion irradiation, even though no discernible degradation in gate leakage current can be measured during irradiation. However, the damage structure has yet to be precisely analyzed. In this article, the nanoscale structure and element distribution of the degradation site in gate leakage current failure devices after post-irradiation gate stress (PIGS) tests were investigated. A gate leakage current failure occurred in PIGS tests of a 1200 V SiC power MOSFET with only 50 V drain bias during irradiation. Further failure analysis using transmission electron microscope (TEM) and energy dispersive X-ray (EDX) revealed a 50-nm wide structural defect in the gate oxide layer directly above the JFET region, which was mainly filled with polysilicon. Suspected latent damage was also observed adjacent to the damaged region. Besides the gate oxide damage, defects were observed on the SiC surface and the polysilicon gate. Through the internal physical response simulation, the picosecond short response time of the electric field in the gate oxide layer can be highly destructive and a critical factor contributing to potential failures at lower drain bias. The diffusion of holes on SiC surfaces causes an extension of the degradation region where the electric field changes.

The gate oxide instability of 4H-SiC pMOS induced by ac stress was experimentally investigated at 200 $^\circ$ C for the first time. The threshold voltage drift ( $\Delta \textit{V}_{\text{th}}$ ) of pMOS under different stress conditions was experimentally measured. The results show that high-frequency ac stress could cause the additional $\Delta \textit{V}_{\text{th}}$ . Furthermore, it was found first that high-frequency ac stress will cause the gate oxide breakdown at 200 $^\circ$ C. However, no gate oxide breakdown was found at 27 $^\circ$ C. By investigating the effects of ac stress conditions on the gate oxide breakdown, it is demonstrated that the captured electrons in interface states at low-level voltage (inversion) play an important role in the gate oxide breakdown.

This article reports the influence of temperature on digital ICs fabricated in 4H-SiC CMOS process technology. The performances of CMOS devices were compared and analyzed at different drain voltages from 25 $^{\circ}$ C to 500 $^{\circ}$ C. The current-output capability of n-channel MOSFET improves with increasing temperature up to 500 $^{\circ}$ C, while that of p-channel MOSFET reaches an optimum at nearly 350 $^{\circ}$ C. The current-output capability of n-channel MOSFET is limited to lower than that of p-channel MOSFET below a temperature point when the drain voltage rises, due to the velocity saturation of electrons. Furthermore, the value of temperature point increases with higher drain voltage. A typical inverter was characterized and analyzed in detail based on the characteristics of CMOS devices. The fall/rise time and high-to-low/low-to-high propagation delay time show a similar temperature characteristic of the drain current of n-and p-channel MOSFETs, respectively. Compared to fall and rise times, the high-to-low and low-to-high propagation delay times intersect at a higher temperature because of the different drain voltages when extracting parameters. The temperature characteristics, including the oscillation frequency of ring oscillators and the output current of gate driver, were also analyzed through the performances of CMOS devices.

In this paper, new electrothermal characteristics degradation and failure mechanism of Silicon carbide junction barrier Schottky (SiC JBS) devices with different die attach materials under 300°C power cycle stress were investigated and found based on thermal structure function and failure analysis. The results showed that the electrothermal characteristics (thermal resistance, R _{th j-d} and on-resistance, R _on ) were consistent, which were different in that decreased firstly and then increased for nanosilver, but increased overall for alloy solders under 300°C PC, both strongly related to evolution of porosity, secondphase, interface cracks, grain size in the die attach layer. However, the electrothermal characteristics were affected by dieattach evolution to varying degrees due to different diffusion mechanisms, causing different failure phenomena (50, 1200 and 4000 failure cycles for high-lead, Au-Ge solder and nanosilver respectively). Meanwhile, the reverse leakage current ( I _R ) and breakdown voltage ( V _R ) variations mainly depended on chip interface states, including the Schottky barrier lowering effect (induced by AlW IMC and large cracks generated at the Schottky contact metal layer/chip interface) and electrons and holes trapped at the SiO ₂ /4H-SiC interface in the termination zone. Finally, this article discussed three failure mechanisms observed in devices employing three die attach materials under 300°C PC.

This paper presents observations of SiC damage related to single-event gate oxide damage in SiC MOSFETs subjected to varying drain biases following heavy-ion irradiation and electrical stress. At low and medium drain biases, both surface melted and lattice damages in SiC were detected by transmission electron microscopy (TEM). While at high drain bias, crack damage propagation into the epilayer was observed directly by Scanning electron microscopy (SEM). Despite the differing types of observed SiC damage, all were confined beneath the gate oxide damage or latent damage induced by heavy ion strikes. Numerical simulations indicate that after gate oxide rupture, the formation of a gate-drain leakage path increases the current beneath the damaged oxide, leading to localized heating and subsequent SiC degradation and damage. These findings provide valuable insights for understanding the failure mechanisms of SiC MOSFETs subjected to single-event failures.