A simple and robust “cell-based” method is presented for the design of variable-gain amplifiers (VGAs). The proposed unit cell utilizes a unique gain compensation method and achieves accurate dB-linear characteristic across a wide tuning range with low power consumption and wide bandwidth. Several such highly dB-linear unit cells can be cascaded to provide the required gain range for a VGA. To prove the concept, single-cell, 5-cell, 10-cell and 15-cell reconfigurable VGAs were fabricated in a standard 0.18 μm CMOS technology. The measurement results show that the 10-cell VGA achieves a gain range of 38.6 dB with less than 0.19 dB gain error. The 15-cell VGA can either be used as reconfigurable VGA for analog control voltage or tunable PGA for digital control stream, with the flexibility of scaling gain range, gain error/step and power consumption. For the VGA at highest gain setting, it consumes 1.12 mW and achieves a gain range of 56 dB, gain error less than 0.3 dB.

A fully integrated 60 GHz frequency synthesizer with an in-phase injection-coupled quadrature voltage-controlled oscillator (IPIC-QVCO) is proposed. Through a particular symmetrical coupling network formed by diode-connected transistors, the in-phase coupling is realized in the IPIC-QVCO, which reduces both phase noise and phase error. A compact inductor-less divider chain is designed to reduce power consumption. A self-correcting low spur charge pump is employed to reduce reference spur. A standalone 60 GHz IPIC-QVCO and a fully integrated PLL are implemented in standard 65 nm low power CMOS technology. The measurement results show that the QVCO covers a frequency range from 57.88 to 68.33 GHz while consuming 11.4 mW power from a 1.2 V supply. The phase noise of the QVCO is -92 ~ -95 dBc/Hz at 1 MHz offset. The FOM and FOM T of the QVCO are -178.1 ~ -179.7 and -182.5 ~ -184.1 dBc/Hz respectively. The tuning range of the frequency synthesizer is from 57.9 to 68.3 GHz, and the power consumption is 24.6 mW. The phase noise of the frequency synthesizer is -89.8 ~ -91.5 dBc/Hz at 1 MHz offset across the frequency band.

A higher frequency, over 2 GHz, is suggested for current 4G or 5G wideband applications. By adopting a unique gain control method, an analog-controlled variable-gain amplifier (VGA) with an accurate dB-linear characteristic is presented. The designed VGA not only features large bandwidth, but also has accurate gain adjustment with a relatively wide control voltage range. The VGA has a measured gain range of 24 dB, of which 17.3 dB is dB-linear with less than ±0.3-dB gain error. The -3-dB bandwidth is relatively constant from 2 to 2.2 GHz for the entire dB-linear range. An output 1-dB compression point of 1.8 dBm and a noise figure of 24 dB are measured. Due to the simple structure, the current consumption of the VGA core is only 2.9 mA from a 1.2-V supply, and the size is only 225 μm×45 μm, excluding pads. Moreover, the robustness of the designed VGA is verified by means of Monte Carlo simulation.

In this letter, an on-chip miniaturized bandpass filter (BPF) is presented, which is based on a grounded center-tapped ring resonator (CTRR) with shunt capacitive loading. To analyze the principle of this design, a simple but effective equivalent circuit model is provided. Using this model, it is easy to show that the CTRR-based approach has a potential to generate two transmission poles within the passband. Compared with the conventional single-pole-based approach, this dual-pole design not only possesses a flexibility of controlling the passband width, but also has better flatness of insertion loss in the passband. In addition, this approach is able to significantly improve the stopband performance. To further demonstrate the feasibility of this approach in practice, the structure is implemented and fabricated in a commercial 0.13-μm (Bi)-CMOS SiGe technology. The measured results show that the BPF has a center frequency at 33 GHz with a bandwidth of 42.4%. The minimum insertion loss is 2.6 dB, while the stopband rejection is maintained to be better than 20 dB beyond 58 GHz. The chip, excluding the pads, is very compact at only 0.03 mm ² (0.11 × 0.28 mm ² ).

In this article, the design of a power amplifier (PA) using a simple but effective architecture, namely, load-modulated balanced amplifier (LMBA), is presented. Using this architecture for PA design, it can achieve not only a relatively high saturated output power but also an excellent efficiency enhancement at the power back-off (PBO) region. To prove that the presented approach is feasible in practice, a PA is designed in a 1- μm gallium arsenide (GaAs) HBT process. Operating under a 5-V power supply, the PA can deliver more than 31-dBm saturated output power with 36% collector efficiency (CE) at 5 GHz. Moreover, it also achieves 1.2 and 1.23 times CE enhancement over an idealistic Class-B PA at 6- and 9-dB PBO levels, respectively. Finally, the designed PA supports 64-quadrature amplitude modulation (QAM) with 80 Msys/s at 22-dBm average output power while still maintaining an error vector magnitude (EVM) and adjacent channel power ratio (ACPR) better than -29.5 dB and -29.4 dBc, respectively.

This letter presents a simple approach for ultra-low-power and high-frequency variable gain amplifier (VGA) design, which requires no additional circuitry to generate the exponential-like function. Thus, the power consumption and chip area of the designed VGA can be drastically reduced without deterioration of other performance. The inverse exponential-like dB-linear characteristic is achieved by utilizing a pair of complementary transistors as the load. The p-MOS transistor is self-biased in the saturation region, while the n-MOS transistor is biased in the sub-threshold region. To prove the concept, a five-cell VGA is fabricated in a standard 0.18 μm CMOS technology. The measurements show that the power consumption of the VGA is less than 150 μW and achieves a total gain range of 71 dB, out of which 45 dB is dB-linear with less than 1 dB gain error, as well as bandwidth of more than 50 MHz. The output P 1 dB is better than 0 dBm and the minimum input-referred noise is 7.5 nV/√(Hz).