JEFFERSON HORA

Dr. JEFFERSON HORA

orcid

Research Focus & Metrics

Academic Career Length

9Years (2018-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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14 January 2021 in IEEE Journal of Solid-State Circuits
Verified
Journal Article
Closed access
LCLang Chen
Lang Chen
HLHang Liu
Hang Liu
JEFFERSON HORAJEFFERSON HORA
JEFFERSON HORA
AZAndrew Zhang
Andrew Zhang
Kiat Seng YeoKiat Seng Yeo
Kiat Seng Yeo
Forest Xi ZhuForest Xi Zhu
Forest Xi Zhu
In this article, the design of a power amplifier (PA) using a simple but effective architecture, namely, load-modulated balanced amplifier (LMBA), is presented. Using this architecture for PA design, it can achieve not only a relatively high saturated output power but also an excellent efficiency enhancement at the power back-off (PBO) region. To prove that the presented approach is feasible in practice, a PA is designed in a 1- μm gallium arsenide (GaAs) HBT process. Operating under a 5-V power supply, the PA can deliver more than 31-dBm saturated output power with 36% collector efficiency (CE) at 5 GHz. Moreover, it also achieves 1.2 and 1.23 times CE enhancement over an idealistic Class-B PA at 6- and 9-dB PBO levels, respectively. Finally, the designed PA supports 64-quadrature amplitude modulation (QAM) with 80 Msys/s at 22-dBm average output power while still maintaining an error vector magnitude (EVM) and adjacent channel power ratio (ACPR) better than -29.5 dB and -29.4 dBc, respectively.

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Journal Article
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JEFFERSON HORAJEFFERSON HORA
JEFFERSON HORA
GPGene Fe Palencia
Gene Fe Palencia
RSRochelle Sabarillo
Rochelle Sabarillo
JTJohnny Romasasa Tugahan
Johnny Romasasa Tugahan
Yichuang SunYichuang Sun
Yichuang Sun
Forest Xi ZhuForest Xi Zhu
Forest Xi Zhu
In rectifier design, the key parameters are the voltage–conversion ratio and the power conversion efficiency. A new circuit design approach is presented in which a capacitor-based, cross-coupled, differential-driven topology is used to boost the voltage–conversion ratio. The scheme also integrates an auxiliary current path to raise the power conversion efficiency. To demonstrate its practicality, two three-stage rectifiers were designed and fabricated using standard 65 nm CMOS technology. The designs were tested under various conditions to assess their performance. The first rectifier targets indoor light energy harvesting applications. It achieves a peak voltage conversion ratio of 3.94 and a maximum power conversion efficiency of 58.7% when driving a 600 Ω load, while supplying over 2 mA of output current. The second rectifier is optimized for RF energy harvesting at 2.4 GHz. Experimental results indicate that it can deliver 70 µA to a 50 kΩ load, with a peak voltage conversion ratio of 5 and a power conversion efficiency of 17.5%.

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MLMichelle Lopez Libang
Michelle Lopez Libang
KAKriz Kevin Adrivan
Kriz Kevin Adrivan
JEFFERSON HORAJEFFERSON HORA
JEFFERSON HORA
CACharade G. Avondo
Charade G. Avondo
Robert ComalingRobert Comaling
Robert Comaling
Yichuang SunYichuang Sun
Yichuang Sun
This paper presents a self-contained startup charging circuit designed for energy-harvesting batteryless IoT devices. The proposed circuit consists of a current-biasing block, a current mirror, a reference voltage generator, and a comparator circuit. The current-biasing circuit drives the current mirror, which supplies the charging current to the energy storage element. Simultaneously, the reference voltage generator—also biased by the current source—produces a stable DC reference voltage. When the energy storage device (e.g., a supercapacitor) lacks sufficient charge, the comparator enables the charging path by activating the current-biasing and mirror circuits. Once adequate energy is stored, the comparator disables these circuits to prevent overcharging. This self-contained solution is intended to autonomously initialize and manage the cold-start charging process in energy-harvesting systems without relying on external controllers. This paper highlights the circuit architecture and validated performance, demonstrating a charging current of up to 27 mA, a reference voltage of 700 mV, and an operating range from 0.9 V to 1.8 V across a temperature range of −40 °C to 85 °C.

30 November 2018 in Journal of Engineering and Technological Sciences
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Journal Article
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DMDarwin C. Mangca
Darwin C. Mangca
OGOlga Joy Gerasta
Olga Joy Gerasta
ALAnne Lorraine Luna
Anne Lorraine Luna
XZXi Zhu
Xi Zhu
JEFFERSON HORAJEFFERSON HORA
JEFFERSON HORA
This paper presents a new approach to linearity testing of analog-to-digital converters (ADCs) through on-the-fly computation in field-programmable gate array (FPGA) hardware. The proposed method computes the linearity while it is processing without compromising the accuracy of the measurement, so very little overhead time is required to compute the final linearity. The results will be displayed immediately after a single ramp is supplied to the device under test. This is a cost-effective chip testing solution for semiconductor companies, achieved by reducing computing time and utilization of low-cost and low-specification automatic test equipment (ATE). The experimental results showed that the on-the-fly computation method significantly reduced the computation time (up to 44.4%) compared to the conventional process. Thus, for every 100M 12-bit ADC tested with 32 hits per code, the company can save up to 139,972 Php on electricity consumption.

1 October 2025
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Book Chapter
Closed access
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JEFFERSON HORAJEFFERSON HORA
JEFFERSON HORA
JGJohn Michael A. Gorospe
John Michael A. Gorospe
GPGene Fe P. Palencia
Gene Fe P. Palencia

1 October 2025
Verified
Book Chapter
Closed access
PDF file
AJAbdul Aziz J. Javier
Abdul Aziz J. Javier
HHHasim D. Habib
Hasim D. Habib
MUMohammad Gaffar U. Umpa
Mohammad Gaffar U. Umpa
GPGene Fe P. Palencia
Gene Fe P. Palencia
JEFFERSON HORAJEFFERSON HORA
JEFFERSON HORA