This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications.

This article presents a two-step analog-to-digital converter (ADC) that operates its first-stage successive approximation register (SAR) ADC in the continuous-time (CT) domain. It avoids the front-end sample-and-hold (S/H) circuit and its associated sampling noise. Hence, the proposed ADC allows the input capacitor size to be substantially reduced without incurring large sampling noise penalty. With input ac coupling, the first-stage CT-SAR can simultaneously perform input tracking and SAR quantization. Its conversion error is minimized by accelerating the SAR speed and providing redundancy. A floating-inverter-based (FIB) dynamic amplifier (DA) is used as the inter-stage amplifier and acts as a low-pass filter for the first-stage residue. To verify the proposed techniques, a 13-bit prototype ADC is built in 40-nm CMOS process. Its input capacitor is only 120 fF, which is over 20 times smaller than what would be needed in a classic Nyquist ADC with the S/H circuit. Operating at 2 MS/s, it achieves 72-dB signal-to-noise-and-distortion-ratio (SNDR) at the Nyquist rate while consuming only 25 μW of power and 0.01 mm² of area.

This work presents an always-on reference ripple cancellation technique that actively cancels the reference settling error throughout the entire SAR conversion process. Unlike the conventional designs that require high-speed reference buffers or large on-chip decoupling capacitors to minimize the error, it incorporates an extra path to actively cancel the error, which can provide considerable reference ripple tolerance, thus significantly relaxing the reference settling requirement. To verify the proposed technique, a prototype 10-bit 100-MS/s SAR ADC is fabricated in a 40-nm CMOS process. Equipped with the proposed technique, it only requires a 0.5-pF decoupling capacitor and an on-chip low-power reference buffer consuming 0.26-mW static power. The proposed technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL) and differential non-linearity (DNL) by 15 times. Overall, the prototype ADC achieves an SNDR of 56.3 dB at Nyquist rate while consuming 1.4 mW, including on-chip reference buffers.

This article presents a 12-bit 1.5-GS/s single-channel pipelined successive approximation register (SAR) analog-to-digital converter (ADC). The ADC leverages a pipelined residue amplification (RA) stage scheme, early quantization technique, and fast differential ring amplifier (ringamp) to achieve high speed and high power efficiency simultaneously. The pipelined RA stage scheme allows the RA and SAR conversion to run in parallel for a fast pipelining operation and a relaxed residue amplifier’s bandwidth requirement, thus alleviating the speed bottleneck of the pipelined SAR ADCs. The early quantization technique reduces the timing budget of the SAR conversion phase, thereby further improving the ADC speed. The differential ringamp with a short settling time and low common-mode gain guarantees the high accuracy and high speed of the critical RA. Furthermore, a flexible digital-to-analog-converter (DAC) topology combining the scaling capacitor and bridge capacitor is employed to align the quantization range avoiding large overheads. The prototype ADC was fabricated in a 28-nm CMOS process and consumes 21.3 mW at 1.5 GS/s. The signal-to-noise-and-distortion-ratio (SNDR) and spurious-free dynamic range (SFDR) are 58.5 and 74.5 dB with a Nyquist input, respectively, achieving a Walden figure-of-merit (FoM) of 20.7 fJ/conversion step and a Schreier FoM of 164 dB.

This article presents a reference ripple cancellation technique for high-speed successive approximation register analog-to-digital converters (SAR ADCs) to address the reference voltage settling issue. Unlike prior techniques that aim to minimize the reference ripple, this article proposes a new perspective: it provides an extra path for the full-sized reference ripple to couple to the comparator but with an opposite polarity, so that the effect of the reference ripple is canceled out, thus ensuring an accurate conversion result. To verify the proposed technique, a prototype 10-bit 120-MS/s SAR ADC is fabricated in a 40-nm CMOS process. The proposed ripple cancellation technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL)/differential non-linearity (DNL) by ten times. Overall, the ADC achieves an SNDR of 55 dB with only 3-pF reference decoupling capacitor.

This brief presents a digital background calibration technique for timing skew in time-interleaved (TI) analog-to-digital converters (ADCs). It updates the calibration step adaptively based on the detection error. This results in large update step initially, and it reduces with the calibration cycle going on. More than two times convergence time is saved compared with the conventional fixed update step method. Besides, by extending the compensation to second-order, both calibration range and accuracy are improved. To demonstrate the effectiveness of the proposed timing skew calibration, extensive simulation and measurement results are provided. It shows that after timing skew calibration, the signal-to-noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) of a two-channel prototype TI ADC are improved by 8.2 and 14.9 dB, respectively.