A 15-bit self-timed incremental analog-to-digital converter (ADC) for event-driven applications is presented. It is based on an asynchronous zoom ADC structure and a fully differential self-timed dynamic-amplifier (DA)-based integrator. Dynamic element matching (DEM) and chopping techniques mitigate the mismatch and noise. Measurements show that the ADC without oversampled clock achieves 93-dB SNR in a conversion time of 0.37 ms while consuming only 4.96- $\mu \text{A}$ current from a 1-V supply. This corresponds to a Schreier FoM of 177.3 dB. The 0.23-mm2 chip was fabricated in a standard 55-nm CMOS process.

This article presents an energy-efficient BJT-based temperature sensor. The output of sensing front-ends is modulated by employing an incremental $\Delta$-$\mathsf{\Sigma }$ ADC as a readout interface. The cascoded floating-inverter-based dynamic amplifier (FIA) is used as the integrator instead of the conventional operational transconductance amplifier (OTA) to achieve a low power consumption. To enhance the accuracy, chopping and dynamic element matching (DEM) are applied to eliminate the component mismatch error while $\beta$-compensation resistor and optimized bias current are used to minimize the effect of $\beta$ variation. Fabricated in a standard 180-nm CMOS process, this sensor has an active area of 0.13 mm${}^2$. While dissipating only 45.7 $\mathsf{\mu }$W in total, the sensor achieves an inaccuracy of ±0.8 °C (3$\sigma$) from −50 °C to 150 °C after one-point calibration.

This paper proposes a fully dynamic zoom ADC, which uses the residue feedforward technique to reduce the “fuzz” caused by the coarse SAR ADC’s quantization noise leakage in free running mode, and uses the extended counting technique to obtain the quantization error in incremental mode. The zoom ADC achieves high resolution in both modes. An improved cascoded floating-inverter-amplifier based integrator is used for low power and fully dynamic conversion. Fabricated in a standard 180nm CMOS process, the zoom ADC occupies an active area of 0.204mm, and consumes less than 1μW while achieving 102.1dB and 97.6dB SNDR in 95Hz bandwidth (BW) in free-running and incremental modes, respectively, corresponding to 182.2dB and 177.5dB FoMSNDR.

This paper presents a fully dynamic incremental ΔΣ ADC for multi-channel simultaneous sampling systems. By using the code division multiplexing technique, a single incremental ΔΣ ADC core can sample the 4-channel signals meanwhile preserving the temporal information. Furthermore, to support various bandwidths with scalable power consumption, a fully dynamic cascoded floating-inverter-amplifier based integrator is used. The proposed 4-channel ADC is fabricated in a standard 180nm CMOS process and only occupies an area of 0.028mm2 per channel. The ADC achieves an SNDR of 80dB within a scalable bandwidth from 1.52kHz to 8.78kHz with power scaling from 56μW to 295μW for each channel. This results in a 154.7dB Schreier FoM within the scaling range.

SRAM stability is a major concern in nanometer CMOS technologies. As the most important metrics of SRAM static stability, the static characteristics of SRAM are derived by static characteristic curves (read butterfly curve, standby butterfly curve, read N curve, write N curve and WNM curve). This paper deduces the read butterfly curve transfer function as an example to show the effect of supply voltage deviation. In order to increase the quantity of SRAM DUTs (Device under Tests) and test accuracy, we propose a test method with VDD correction which eliminates the effect of supply voltage deviation. First, an addressable test structure is applied, where the transmission gates are used to force and sense the node voltages, and then correct the voltages. Second, a test algorithm with fast convergence combining the bisection method and PID (Proportion Integral Differential) algorithm is proposed to correct the voltages. SPICE simulations show that the proposed method reduces the error from approximately 10% (commonly used methods) to less than 2%. It is further implemented in a standard 55nm CMOS process, and the static characteristic curves of 1k-bits SRAM DUTs are measured within the accuracy range of 1 mV, which fit well with the simulation results, indicating the method can accurately measure 1k-bits DUTs.

This article presents a photovoltaic energy harvester (PVEH) that achieves high maximum power point tracking (MPPT) efficiency and power conversion efficiency across a $100~000{\times }$ input power dynamic range (DR) (from $10~{\mu }$ W to 1W). Wide-dynamic-range operation is challenging due to the inherent tradeoff between MPPT accuracy and controller power consumption. To address this, an adaptive power-scalable MPPT scheme is proposed, employing a direct power-to-digital converter (PDC) that eliminates the need for current sensing, analog multipliers, or lookup tables (LUTs). The PDC utilizes an equivalent power comparison technique, minimizing its power consumption. The MPPT controller autonomously scales its power, consuming minimal energy in low-irradiation conditions while maintaining high tracking accuracy and speed in high-irradiation conditions. Furthermore, a multiple-counting technique mitigates comparator noise and settling errors. Implemented in a 180-nm CMOS process, the harvester achieves a peak MPPT efficiency of 99.9% and maintains >98% across the entire range, representing a $10{\times }$ improvement in DR over prior art. It also achieves a competitive power conversion efficiency of >82% (peak of 92%) over the same DR.